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[Qemu-devel] [PULL 13/25] sdhci: add i.MX SD Stable Clock bit
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 13/25] sdhci: add i.MX SD Stable Clock bit |
Date: |
Mon, 20 Aug 2018 11:32:00 +0100 |
From: Hans-Erik Floryd <address@hidden>
Add the ESDHC PRSSTAT_SDSTB bit, using the value of SDHC_CLOCK_INT_STABLE.
Freescale recommends checking this bit when changing clock frequency.
Signed-off-by: Hans-Erik Floryd <address@hidden>
Message-id: address@hidden
[PMM: fixed indentation]
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
hw/sd/sdhci-internal.h | 2 ++
hw/sd/sdhci.c | 8 ++++++++
2 files changed, 10 insertions(+)
diff --git a/hw/sd/sdhci-internal.h b/hw/sd/sdhci-internal.h
index 756ef3f3c2e..19665fd4013 100644
--- a/hw/sd/sdhci-internal.h
+++ b/hw/sd/sdhci-internal.h
@@ -302,4 +302,6 @@ extern const VMStateDescription sdhci_vmstate;
#define ESDHC_CTRL_4BITBUS (0x1 << 1)
#define ESDHC_CTRL_8BITBUS (0x2 << 1)
+#define ESDHC_PRNSTS_SDSTB (1 << 3)
+
#endif
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
index 8f58c31265a..81bbf032794 100644
--- a/hw/sd/sdhci.c
+++ b/hw/sd/sdhci.c
@@ -1651,6 +1651,14 @@ static uint64_t usdhc_read(void *opaque, hwaddr offset,
unsigned size)
break;
+ case SDHC_PRNSTS:
+ /* Add SDSTB (SD Clock Stable) bit to PRNSTS */
+ ret = sdhci_read(opaque, offset, size) & ~ESDHC_PRNSTS_SDSTB;
+ if (s->clkcon & SDHC_CLOCK_INT_STABLE) {
+ ret |= ESDHC_PRNSTS_SDSTB;
+ }
+ break;
+
case ESDHC_DLL_CTRL:
case ESDHC_TUNE_CTRL_STATUS:
case ESDHC_UNDOCUMENTED_REG27:
--
2.18.0
- [Qemu-devel] [PULL 00/25] target-arm queue, Peter Maydell, 2018/08/20
- [Qemu-devel] [PULL 07/25] target/arm: Implement AArch32 HVBAR, Peter Maydell, 2018/08/20
- [Qemu-devel] [PULL 06/25] target/arm: Add missing .cp = 15 to HMAIR1 and HAMAIR1 regdefs, Peter Maydell, 2018/08/20
- [Qemu-devel] [PULL 05/25] target/arm: Correct typo in HAMAIR1 regdef name, Peter Maydell, 2018/08/20
- [Qemu-devel] [PULL 04/25] imx_serial: Generate interrupt on receive data ready if enabled, Peter Maydell, 2018/08/20
- [Qemu-devel] [PULL 08/25] target/arm: Implement AArch32 Hyp FARs, Peter Maydell, 2018/08/20
- [Qemu-devel] [PULL 11/25] target/arm: Implement AArch32 ERET instruction, Peter Maydell, 2018/08/20
- [Qemu-devel] [PULL 10/25] target/arm: Permit accesses to ELR_Hyp from Hyp mode via MSR/MRS (banked), Peter Maydell, 2018/08/20
- [Qemu-devel] [PULL 13/25] sdhci: add i.MX SD Stable Clock bit,
Peter Maydell <=
- [Qemu-devel] [PULL 12/25] hw/arm/virt: Add virt-3.1 machine type, Peter Maydell, 2018/08/20
- [Qemu-devel] [PULL 03/25] hw/intc/arm_gicv3_its: downgrade error_report to warn_report in kvm_arm_its_reset, Peter Maydell, 2018/08/20
- [Qemu-devel] [PULL 17/25] hw/timer/m48t59: Move away from old_mmio accessors, Peter Maydell, 2018/08/20
- [Qemu-devel] [PULL 14/25] hw/ssi/xilinx_spips: Remove unneeded MMIO request_ptr code, Peter Maydell, 2018/08/20
- [Qemu-devel] [PULL 09/25] target/arm: Implement ESR_EL2/HSR for AArch32 and no-EL2, Peter Maydell, 2018/08/20
- [Qemu-devel] [PULL 16/25] hw/misc: Remove mmio_interface device, Peter Maydell, 2018/08/20
- [Qemu-devel] [PULL 19/25] nvic: Expose NMI line, Peter Maydell, 2018/08/20
- [Qemu-devel] [PULL 02/25] docs/generic-loader: mention U-Boot and Intel HEX executable formats, Peter Maydell, 2018/08/20
- [Qemu-devel] [PULL 01/25] target/arm: Fix crash on conditional instruction in an IT block, Peter Maydell, 2018/08/20
- [Qemu-devel] [PULL 15/25] memory: Remove MMIO request_ptr APIs, Peter Maydell, 2018/08/20