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[Qemu-devel] [PULL 11/25] target/arm: Implement AArch32 ERET instruction
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 11/25] target/arm: Implement AArch32 ERET instruction |
Date: |
Mon, 20 Aug 2018 11:31:58 +0100 |
ARMv7VE introduced the ERET instruction, which is necessary to
return from an exception taken to Hyp mode. Implement this.
In A32 encoding it is a completely new encoding; in T32 it
is an adjustment of the behaviour of the existing
"SUBS PC, LR, #<imm8>" instruction.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Luc Michel <address@hidden>
Message-id: address@hidden
---
target/arm/translate.c | 31 +++++++++++++++++++++++++++++--
1 file changed, 29 insertions(+), 2 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 8405c08fd1a..bcfc29c5a6a 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -8901,6 +8901,25 @@ static void disas_arm_insn(DisasContext *s, unsigned int
insn)
tcg_temp_free_i32(tmp2);
store_reg(s, rd, tmp);
break;
+ case 0x6: /* ERET */
+ if (op1 != 3) {
+ goto illegal_op;
+ }
+ if (!arm_dc_feature(s, ARM_FEATURE_V7VE)) {
+ goto illegal_op;
+ }
+ if ((insn & 0x000fff0f) != 0x0000000e) {
+ /* UNPREDICTABLE; we choose to UNDEF */
+ goto illegal_op;
+ }
+
+ if (s->current_el == 2) {
+ tmp = load_cpu_field(elr_el[2]);
+ } else {
+ tmp = load_reg(s, 14);
+ }
+ gen_exception_return(s, tmp);
+ break;
case 7:
{
int imm16 = extract32(insn, 0, 4) | (extract32(insn, 8, 12) << 4);
@@ -11158,8 +11177,16 @@ static void disas_thumb2_insn(DisasContext *s,
uint32_t insn)
if (rn != 14 || rd != 15) {
goto illegal_op;
}
- tmp = load_reg(s, rn);
- tcg_gen_subi_i32(tmp, tmp, insn & 0xff);
+ if (s->current_el == 2) {
+ /* ERET from Hyp uses ELR_Hyp, not LR */
+ if (insn & 0xff) {
+ goto illegal_op;
+ }
+ tmp = load_cpu_field(elr_el[2]);
+ } else {
+ tmp = load_reg(s, rn);
+ tcg_gen_subi_i32(tmp, tmp, insn & 0xff);
+ }
gen_exception_return(s, tmp);
break;
case 6: /* MRS */
--
2.18.0
- [Qemu-devel] [PULL 00/25] target-arm queue, Peter Maydell, 2018/08/20
- [Qemu-devel] [PULL 07/25] target/arm: Implement AArch32 HVBAR, Peter Maydell, 2018/08/20
- [Qemu-devel] [PULL 06/25] target/arm: Add missing .cp = 15 to HMAIR1 and HAMAIR1 regdefs, Peter Maydell, 2018/08/20
- [Qemu-devel] [PULL 05/25] target/arm: Correct typo in HAMAIR1 regdef name, Peter Maydell, 2018/08/20
- [Qemu-devel] [PULL 04/25] imx_serial: Generate interrupt on receive data ready if enabled, Peter Maydell, 2018/08/20
- [Qemu-devel] [PULL 08/25] target/arm: Implement AArch32 Hyp FARs, Peter Maydell, 2018/08/20
- [Qemu-devel] [PULL 11/25] target/arm: Implement AArch32 ERET instruction,
Peter Maydell <=
- [Qemu-devel] [PULL 10/25] target/arm: Permit accesses to ELR_Hyp from Hyp mode via MSR/MRS (banked), Peter Maydell, 2018/08/20
- [Qemu-devel] [PULL 13/25] sdhci: add i.MX SD Stable Clock bit, Peter Maydell, 2018/08/20
- [Qemu-devel] [PULL 12/25] hw/arm/virt: Add virt-3.1 machine type, Peter Maydell, 2018/08/20
- [Qemu-devel] [PULL 03/25] hw/intc/arm_gicv3_its: downgrade error_report to warn_report in kvm_arm_its_reset, Peter Maydell, 2018/08/20
- [Qemu-devel] [PULL 17/25] hw/timer/m48t59: Move away from old_mmio accessors, Peter Maydell, 2018/08/20
- [Qemu-devel] [PULL 14/25] hw/ssi/xilinx_spips: Remove unneeded MMIO request_ptr code, Peter Maydell, 2018/08/20
- [Qemu-devel] [PULL 09/25] target/arm: Implement ESR_EL2/HSR for AArch32 and no-EL2, Peter Maydell, 2018/08/20
- [Qemu-devel] [PULL 16/25] hw/misc: Remove mmio_interface device, Peter Maydell, 2018/08/20
- [Qemu-devel] [PULL 19/25] nvic: Expose NMI line, Peter Maydell, 2018/08/20
- [Qemu-devel] [PULL 02/25] docs/generic-loader: mention U-Boot and Intel HEX executable formats, Peter Maydell, 2018/08/20