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[Qemu-devel] [PULL 38/52] hw/ssi/pl022: Correct wrong DMACR and ICR hand
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 38/52] hw/ssi/pl022: Correct wrong DMACR and ICR handling |
Date: |
Fri, 24 Aug 2018 10:33:29 +0100 |
In the PL022, register offset 0x20 is the ICR, a write-only
interrupt-clear register. Register offset 0x24 is DMACR, the DMA
control register. We were incorrectly implementing (a stub version
of) DMACR at 0x20, and not implementing anything at 0x24. Fix this
bug.
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Reviewed-by: Richard Henderson <address@hidden>
---
hw/ssi/pl022.c | 12 ++++++++++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/hw/ssi/pl022.c b/hw/ssi/pl022.c
index d310671d18e..e58247554cc 100644
--- a/hw/ssi/pl022.c
+++ b/hw/ssi/pl022.c
@@ -146,7 +146,7 @@ static uint64_t pl022_read(void *opaque, hwaddr offset,
return s->is;
case 0x1c: /* MIS */
return s->im & s->is;
- case 0x20: /* DMACR */
+ case 0x24: /* DMACR */
/* Not implemented. */
return 0;
default:
@@ -192,7 +192,15 @@ static void pl022_write(void *opaque, hwaddr offset,
s->im = value;
pl022_update(s);
break;
- case 0x20: /* DMACR */
+ case 0x20: /* ICR */
+ /*
+ * write-1-to-clear: bit 0 clears ROR, bit 1 clears RT;
+ * RX and TX interrupts cannot be cleared this way.
+ */
+ value &= PL022_INT_ROR | PL022_INT_RT;
+ s->is &= ~value;
+ break;
+ case 0x24: /* DMACR */
if (value) {
qemu_log_mask(LOG_UNIMP, "pl022: DMA not implemented\n");
}
--
2.18.0
- [Qemu-devel] [PULL 25/52] hw/arm/iotkit: Wire up the S32KTIMER, (continued)
- [Qemu-devel] [PULL 25/52] hw/arm/iotkit: Wire up the S32KTIMER, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 26/52] hw/misc/iotkit-sysctl: Implement IoTKit system control element, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 28/52] hw/misc/iotkit: Wire up the sysctl and sysinfo register blocks, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 27/52] hw/misc/iotkit-sysinfo: Implement IoTKit system information block, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 31/52] hw/arm/iotkit: Wire up the lines for MSCs, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 32/52] hw/arm/mps2-tz: Create PL081s and MSCs, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 30/52] hw/misc/iotkit-secctl: Wire up registers for controlling MSCs, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 33/52] hw/ssi/pl022: Allow use as embedded-struct device, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 29/52] hw/misc/tz-msc: Model TrustZone Master Security Controller, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 37/52] hw/ssi/pl022: Correct wrong value for PL022_INT_RT, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 38/52] hw/ssi/pl022: Correct wrong DMACR and ICR handling,
Peter Maydell <=
- [Qemu-devel] [PULL 39/52] hw/arm/mps2-tz: Instantiate SPI controllers, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 43/52] target/arm: Remove a handful of stray tabs, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 40/52] hw/arm/mps2-tz: Fix MPS2 SCC config register values, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 42/52] target/arm: Untabify iwmmxt_helper.c, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 36/52] hw/ssi/pl022: Use DeviceState::realize rather than SysBusDevice::init, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 34/52] hw/ssi/pl022: Set up reset function in class init, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 47/52] hw/display/bcm2835_fb: Reset resolution, etc correctly, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 46/52] hw/display/bcm2835_fb: Drop unused size and pitch fields, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 49/52] hw/display/bcm2835_fb: Fix handling of virtual framebuffer, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 44/52] hw/misc/bcm2835_fb: Move config fields to their own struct, Peter Maydell, 2018/08/24