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[Qemu-devel] [PATCH 18/35] target/mips: access cpu->interrupt_request wi
From: |
Emilio G. Cota |
Subject: |
[Qemu-devel] [PATCH 18/35] target/mips: access cpu->interrupt_request with atomics |
Date: |
Mon, 17 Sep 2018 12:30:46 -0400 |
From: Paolo Bonzini <address@hidden>
Cc: Aurelien Jarno <address@hidden>
Cc: Aleksandar Markovic <address@hidden>
Cc: James Hogan <address@hidden>
Signed-off-by: Paolo Bonzini <address@hidden>
Signed-off-by: Emilio G. Cota <address@hidden>
---
target/mips/cpu.c | 7 ++++---
target/mips/kvm.c | 2 +-
2 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 497706b669..8d07696825 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -56,11 +56,12 @@ static bool mips_cpu_has_work(CPUState *cs)
MIPSCPU *cpu = MIPS_CPU(cs);
CPUMIPSState *env = &cpu->env;
bool has_work = false;
+ uint32_t interrupt_request = atomic_read(&cs->interrupt_request);
/* Prior to MIPS Release 6 it is implementation dependent if non-enabled
interrupts wake-up the CPU, however most of the implementations only
check for interrupts that can be taken. */
- if ((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
+ if ((interrupt_request & CPU_INTERRUPT_HARD) &&
cpu_mips_hw_interrupts_pending(env)) {
if (cpu_mips_hw_interrupts_enabled(env) ||
(env->insn_flags & ISA_MIPS32R6)) {
@@ -72,7 +73,7 @@ static bool mips_cpu_has_work(CPUState *cs)
if (env->CP0_Config3 & (1 << CP0C3_MT)) {
/* The QEMU model will issue an _WAKE request whenever the CPUs
should be woken up. */
- if (cs->interrupt_request & CPU_INTERRUPT_WAKE) {
+ if (interrupt_request & CPU_INTERRUPT_WAKE) {
has_work = true;
}
@@ -82,7 +83,7 @@ static bool mips_cpu_has_work(CPUState *cs)
}
/* MIPS Release 6 has the ability to halt the CPU. */
if (env->CP0_Config5 & (1 << CP0C5_VP)) {
- if (cs->interrupt_request & CPU_INTERRUPT_WAKE) {
+ if (interrupt_request & CPU_INTERRUPT_WAKE) {
has_work = true;
}
if (!mips_vp_active(env)) {
diff --git a/target/mips/kvm.c b/target/mips/kvm.c
index 8e72850962..71fe3501a8 100644
--- a/target/mips/kvm.c
+++ b/target/mips/kvm.c
@@ -135,7 +135,7 @@ void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run)
qemu_mutex_lock_iothread();
- if ((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
+ if ((atomic_read(&cs->interrupt_request) & CPU_INTERRUPT_HARD) &&
cpu_mips_io_interrupts_pending(cpu)) {
intr.cpu = -1;
intr.irq = 2;
--
2.17.1
- [Qemu-devel] [PATCH 11/35] target/i386: access cpu->interrupt_request with atomics, (continued)
- [Qemu-devel] [PATCH 11/35] target/i386: access cpu->interrupt_request with atomics, Emilio G. Cota, 2018/09/17
- [Qemu-devel] [PATCH 10/35] target/hppa: access cpu->interrupt_request with atomics, Emilio G. Cota, 2018/09/17
- [Qemu-devel] [PATCH 08/35] target/arm: access cpu->interrupt_request with atomics, Emilio G. Cota, 2018/09/17
- [Qemu-devel] [PATCH 02/35] target/i386: use cpu_reset_interrupt, Emilio G. Cota, 2018/09/17
- [Qemu-devel] [PATCH 18/35] target/mips: access cpu->interrupt_request with atomics,
Emilio G. Cota <=
- [Qemu-devel] [PATCH 01/35] tcg: access cpu->icount_decr.u16.high with atomics, Emilio G. Cota, 2018/09/17
- [Qemu-devel] [PATCH 34/35] exec: push BQL down to cpu->do_interrupt, Emilio G. Cota, 2018/09/17
- [Qemu-devel] [PATCH 16/35] target/m68k: access cpu->interrupt_request with atomics, Emilio G. Cota, 2018/09/17
- [Qemu-devel] [PATCH 20/35] target/nios2: access cpu->interrupt_request with atomics, Emilio G. Cota, 2018/09/17