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Re: [Qemu-devel] [PATCH 11/35] target/i386: access cpu->interrupt_reques
From: |
Emilio G. Cota |
Subject: |
Re: [Qemu-devel] [PATCH 11/35] target/i386: access cpu->interrupt_request with atomics |
Date: |
Wed, 19 Sep 2018 11:02:20 -0400 |
User-agent: |
Mutt/1.9.4 (2018-02-28) |
On Tue, Sep 18, 2018 at 14:04:35 -0700, Richard Henderson wrote:
> On 9/17/18 9:30 AM, Emilio G. Cota wrote:
> > cpu_reset(cs);
> > - cs->interrupt_request = sipi;
> > + atomic_mb_set(&cs->interrupt_request, sipi);
> > memcpy(&env->start_init_save, &save->start_init_save,
>
> Why does this need a memory barrier?
>
> Anyway, I think a bare mechanical conversion would be best
> for the first patch and then extra barriers added separately
> and with a description of why.
Almost no corresponding read has a barrier so it's hard to
justify this one. I'll drop it.
Thanks,
Emilio
- Re: [Qemu-devel] [PATCH 07/35] target/alpha: access cpu->interrupt_request with atomics, (continued)
- [Qemu-devel] [PATCH 04/35] target/ppc: use cpu_reset_interrupt, Emilio G. Cota, 2018/09/17
- [Qemu-devel] [PATCH 06/35] exec: use cpu_reset_interrupt, Emilio G. Cota, 2018/09/17
- [Qemu-devel] [PATCH 11/35] target/i386: access cpu->interrupt_request with atomics, Emilio G. Cota, 2018/09/17
- [Qemu-devel] [PATCH 10/35] target/hppa: access cpu->interrupt_request with atomics, Emilio G. Cota, 2018/09/17
- [Qemu-devel] [PATCH 08/35] target/arm: access cpu->interrupt_request with atomics, Emilio G. Cota, 2018/09/17
- [Qemu-devel] [PATCH 02/35] target/i386: use cpu_reset_interrupt, Emilio G. Cota, 2018/09/17
- [Qemu-devel] [PATCH 18/35] target/mips: access cpu->interrupt_request with atomics, Emilio G. Cota, 2018/09/17
- [Qemu-devel] [PATCH 01/35] tcg: access cpu->icount_decr.u16.high with atomics, Emilio G. Cota, 2018/09/17