Re: [Qemu-devel] [PATCH v5 6/8] target/mips: Define the R5900 CPU

[Maciej W. Rozycki]

On Mon, 24 Sep 2018, Philippe Mathieu-Daudé wrote:

> >> >From the DS:
> >>
> >>   The C790 core has the following features:
> >>    - Large on-chip caches
> >>     • Instruction cache: 32KB, 2-way set associative
> >>     • Data cache: 32KB, 2-way set-associative (with write-back protocol)
> >>
> >> 0x2 << CP0C0_K0 is 'Uncached', why you selected this and not 0x3 for
> >> 'Cacheable, write-back, write allocate'?
> > 
> >  No other MIPS emulation does what you suggest, which is why I refrained 
> > from commenting on the K0 field and commented on the ICE/DCE bits only.  
> > See:
> > 
> > /* Have config1, uncached coherency */
> > #define MIPS_CONFIG0                                              \
> >   ((1U << CP0C0_M) | (0x2 << CP0C0_K0))
> > 
> > elsewhere in this file.
> 
> Yes, this was just out of curiosity.

 Also the value of this field at reset is undefined for this CPU (as is 
architecturally, though some implementations might work otherwise), so 0x2 
is as good as any.  For the user emulation mode we could consider choosing 
what the kernel would use, however that would only matter if we had the 
cache properly emulated.

  Maciej