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Re: [Qemu-devel] [PATCH 01/28] targer/riscv: Activate decodetree and imp
From: |
Richard Henderson |
Subject: |
Re: [Qemu-devel] [PATCH 01/28] targer/riscv: Activate decodetree and implemnt LUI & AUIPC |
Date: |
Fri, 12 Oct 2018 11:03:39 -0700 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.0 |
On 10/12/18 10:30 AM, Bastian Koppelmann wrote:
> +#define EX_SH(amount) \
> + static int64_t ex_shift_##amount(int imm) \
> + { \
> + return imm << amount; \
> + }
The int64_t return doesn't help, because it'll be stored back into a struct
that uses just "int". If you have a shift that goes outside that, you'd have
to handle it in the trans_* function. Which is not the case here, at least.
Otherwise,
Reviewed-by: Richard Henderson <address@hidden>
r~
- [Qemu-devel] [PATCH 00/28] target/riscv: Convert to decodetree, Bastian Koppelmann, 2018/10/12
- [Qemu-devel] [PATCH 03/28] target/riscv: Convert RVXI load/store insns to decodetree, Bastian Koppelmann, 2018/10/12
- [Qemu-devel] [PATCH 04/28] target/riscv: Convert RVXI arithmetic insns to decodetree, Bastian Koppelmann, 2018/10/12
- [Qemu-devel] [PATCH 01/28] targer/riscv: Activate decodetree and implemnt LUI & AUIPC, Bastian Koppelmann, 2018/10/12
- Re: [Qemu-devel] [PATCH 01/28] targer/riscv: Activate decodetree and implemnt LUI & AUIPC,
Richard Henderson <=
- [Qemu-devel] [PATCH 07/28] target/riscv: Convert RVXM insns to decodetree, Bastian Koppelmann, 2018/10/12
- [Qemu-devel] [PATCH 06/28] target/riscv: Convert RVXI csr insns to decodetree, Bastian Koppelmann, 2018/10/12
- [Qemu-devel] [PATCH 05/28] target/riscv: Convert RVXI fence insns to decodetree, Bastian Koppelmann, 2018/10/12
- [Qemu-devel] [PATCH 02/28] target/riscv: Convert RVXI branch insns to decodetree, Bastian Koppelmann, 2018/10/12
- [Qemu-devel] [PATCH 08/28] target/riscv: Convert RV32A insns to decodetree, Bastian Koppelmann, 2018/10/12