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[Qemu-devel] [PULL 11/45] target/arm: Improve debug logging of AArch32 e
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 11/45] target/arm: Improve debug logging of AArch32 exception return |
Date: |
Fri, 19 Oct 2018 17:57:01 +0100 |
For AArch32, exception return happens through certain kinds
of CPSR write. We don't currently have any CPU_LOG_INT logging
of these events (unlike AArch64, where we log in the ERET
instruction). Add some suitable logging.
This will log exception returns like this:
Exception return from AArch32 hyp to usr PC 0x80100374
paralleling the existing logging in the exception_return
helper for AArch64 exception returns:
Exception return from AArch64 EL2 to AArch64 EL0 PC 0x8003045c
Exception return from AArch64 EL2 to AArch32 EL0 PC 0x8003045c
(Note that an AArch32 exception return can only be
AArch32->AArch32, never to AArch64.)
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
---
target/arm/internals.h | 18 ++++++++++++++++++
target/arm/helper.c | 10 ++++++++++
target/arm/translate.c | 7 +------
3 files changed, 29 insertions(+), 6 deletions(-)
diff --git a/target/arm/internals.h b/target/arm/internals.h
index a4fc709bcc7..276f2d8a8df 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -840,4 +840,22 @@ static inline uint32_t v7m_sp_limit(CPUARMState *env)
}
}
+/**
+ * aarch32_mode_name(): Return name of the AArch32 CPU mode
+ * @psr: Program Status Register indicating CPU mode
+ *
+ * Returns, for debug logging purposes, a printable representation
+ * of the AArch32 CPU mode ("svc", "usr", etc) as indicated by
+ * the low bits of the specified PSR.
+ */
+static inline const char *aarch32_mode_name(uint32_t psr)
+{
+ static const char cpu_mode_names[16][4] = {
+ "usr", "fiq", "irq", "svc", "???", "???", "mon", "abt",
+ "???", "???", "hyp", "und", "???", "???", "???", "sys"
+ };
+
+ return cpu_mode_names[psr & 0xf];
+}
+
#endif
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 9a0e92f286c..09c31c47418 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -6208,7 +6208,17 @@ void cpsr_write(CPUARMState *env, uint32_t val, uint32_t
mask,
mask |= CPSR_IL;
val |= CPSR_IL;
}
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "Illegal AArch32 mode switch attempt from %s to
%s\n",
+ aarch32_mode_name(env->uncached_cpsr),
+ aarch32_mode_name(val));
} else {
+ qemu_log_mask(CPU_LOG_INT, "%s %s to %s PC 0x%" PRIx32 "\n",
+ write_type == CPSRWriteExceptionReturn ?
+ "Exception return from AArch32" :
+ "AArch32 mode switch from",
+ aarch32_mode_name(env->uncached_cpsr),
+ aarch32_mode_name(val), env->regs[15]);
switch_mode(env, val & CPSR_M);
}
}
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 42dec1f7358..46c4b86bf52 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -13090,11 +13090,6 @@ void gen_intermediate_code(CPUState *cpu,
TranslationBlock *tb)
translator_loop(ops, &dc.base, cpu, tb);
}
-static const char *cpu_mode_names[16] = {
- "usr", "fiq", "irq", "svc", "???", "???", "mon", "abt",
- "???", "???", "hyp", "und", "???", "???", "???", "sys"
-};
-
void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
int flags)
{
@@ -13160,7 +13155,7 @@ void arm_cpu_dump_state(CPUState *cs, FILE *f,
fprintf_function cpu_fprintf,
psr & CPSR_V ? 'V' : '-',
psr & CPSR_T ? 'T' : 'A',
ns_status,
- cpu_mode_names[psr & 0xf], (psr & 0x10) ? 32 : 26);
+ aarch32_mode_name(psr), (psr & 0x10) ? 32 : 26);
}
if (flags & CPU_DUMP_FPU) {
--
2.19.1
- [Qemu-devel] [PULL 01/45] ssi-sd: Make devices picking up backends unavailable with -device, (continued)
- [Qemu-devel] [PULL 01/45] ssi-sd: Make devices picking up backends unavailable with -device, Peter Maydell, 2018/10/19
- [Qemu-devel] [PULL 02/45] target/arm: Add support for VCPU event states, Peter Maydell, 2018/10/19
- [Qemu-devel] [PULL 04/45] target/arm: V8M should not imply V7VE, Peter Maydell, 2018/10/19
- [Qemu-devel] [PULL 06/45] target/arm: Convert division from feature bits to isar0 tests, Peter Maydell, 2018/10/19
- [Qemu-devel] [PULL 07/45] target/arm: Convert jazelle from feature bit to isar1 test, Peter Maydell, 2018/10/19
- [Qemu-devel] [PULL 08/45] target/arm: Convert t32ee from feature bit to isar3 test, Peter Maydell, 2018/10/19
- [Qemu-devel] [PULL 09/45] target/arm: Convert sve from feature bit to aa64pfr0 test, Peter Maydell, 2018/10/19
- [Qemu-devel] [PULL 03/45] target/arm: Move some system registers into a substructure, Peter Maydell, 2018/10/19
- [Qemu-devel] [PULL 05/45] target/arm: Convert v8 extensions from feature bits to isar tests, Peter Maydell, 2018/10/19
- [Qemu-devel] [PULL 10/45] target/arm: Convert v8.2-fp16 from feature bit to aa64pfr0 test, Peter Maydell, 2018/10/19
- [Qemu-devel] [PULL 11/45] target/arm: Improve debug logging of AArch32 exception return,
Peter Maydell <=
- [Qemu-devel] [PULL 21/45] hw/arm/boot: Increase compliance with kernel arm64 boot protocol, Peter Maydell, 2018/10/19
- [Qemu-devel] [PULL 20/45] target/arm: Report correct syndrome for FP/SIMD traps to Hyp mode, Peter Maydell, 2018/10/19
- [Qemu-devel] [PULL 22/45] target/arm: Hoist address increment for vector memory ops, Peter Maydell, 2018/10/19
- [Qemu-devel] [PULL 36/45] target/arm: Use gvec for NEON_3R_VML, Peter Maydell, 2018/10/19
- [Qemu-devel] [PULL 35/45] target/arm: Use gvec for VSRI, VSLI, Peter Maydell, 2018/10/19
- [Qemu-devel] [PULL 38/45] target/arm: Use gvec for NEON VLD all lanes, Peter Maydell, 2018/10/19
- [Qemu-devel] [PULL 45/45] target/arm: Only flush tlb if ASID changes, Peter Maydell, 2018/10/19
- [Qemu-devel] [PULL 44/45] target/arm: Remove writefn from TTBR0_EL3, Peter Maydell, 2018/10/19
- [Qemu-devel] [PULL 43/45] net: cadence_gem: Announce 64bit addressing support, Peter Maydell, 2018/10/19
- [Qemu-devel] [PULL 42/45] net: cadence_gem: Announce availability of priority queues, Peter Maydell, 2018/10/19