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[Qemu-devel] [PULL 22/45] target/arm: Hoist address increment for vector
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 22/45] target/arm: Hoist address increment for vector memory ops |
Date: |
Fri, 19 Oct 2018 17:57:12 +0100 |
From: Richard Henderson <address@hidden>
This can reduce the number of opcodes required for certain
complex forms of load-multiple (e.g. ld4.16b).
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/translate-a64.c | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 09c7c4af047..371909620bb 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -3012,7 +3012,7 @@ static void disas_ldst_multiple_struct(DisasContext *s,
uint32_t insn)
bool is_store = !extract32(insn, 22, 1);
bool is_postidx = extract32(insn, 23, 1);
bool is_q = extract32(insn, 30, 1);
- TCGv_i64 tcg_addr, tcg_rn;
+ TCGv_i64 tcg_addr, tcg_rn, tcg_ebytes;
int ebytes = 1 << size;
int elements = (is_q ? 128 : 64) / (8 << size);
@@ -3077,6 +3077,7 @@ static void disas_ldst_multiple_struct(DisasContext *s,
uint32_t insn)
tcg_rn = cpu_reg_sp(s, rn);
tcg_addr = tcg_temp_new_i64();
tcg_gen_mov_i64(tcg_addr, tcg_rn);
+ tcg_ebytes = tcg_const_i64(ebytes);
for (r = 0; r < rpt; r++) {
int e;
@@ -3101,7 +3102,7 @@ static void disas_ldst_multiple_struct(DisasContext *s,
uint32_t insn)
clear_vec_high(s, is_q, tt);
}
}
- tcg_gen_addi_i64(tcg_addr, tcg_addr, ebytes);
+ tcg_gen_add_i64(tcg_addr, tcg_addr, tcg_ebytes);
tt = (tt + 1) % 32;
}
}
@@ -3115,6 +3116,7 @@ static void disas_ldst_multiple_struct(DisasContext *s,
uint32_t insn)
tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, rm));
}
}
+ tcg_temp_free_i64(tcg_ebytes);
tcg_temp_free_i64(tcg_addr);
}
@@ -3157,7 +3159,7 @@ static void disas_ldst_single_struct(DisasContext *s,
uint32_t insn)
bool replicate = false;
int index = is_q << 3 | S << 2 | size;
int ebytes, xs;
- TCGv_i64 tcg_addr, tcg_rn;
+ TCGv_i64 tcg_addr, tcg_rn, tcg_ebytes;
switch (scale) {
case 3:
@@ -3210,6 +3212,7 @@ static void disas_ldst_single_struct(DisasContext *s,
uint32_t insn)
tcg_rn = cpu_reg_sp(s, rn);
tcg_addr = tcg_temp_new_i64();
tcg_gen_mov_i64(tcg_addr, tcg_rn);
+ tcg_ebytes = tcg_const_i64(ebytes);
for (xs = 0; xs < selem; xs++) {
if (replicate) {
@@ -3252,7 +3255,7 @@ static void disas_ldst_single_struct(DisasContext *s,
uint32_t insn)
do_vec_st(s, rt, index, tcg_addr, scale);
}
}
- tcg_gen_addi_i64(tcg_addr, tcg_addr, ebytes);
+ tcg_gen_add_i64(tcg_addr, tcg_addr, tcg_ebytes);
rt = (rt + 1) % 32;
}
@@ -3264,6 +3267,7 @@ static void disas_ldst_single_struct(DisasContext *s,
uint32_t insn)
tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, rm));
}
}
+ tcg_temp_free_i64(tcg_ebytes);
tcg_temp_free_i64(tcg_addr);
}
--
2.19.1
- [Qemu-devel] [PULL 06/45] target/arm: Convert division from feature bits to isar0 tests, (continued)
- [Qemu-devel] [PULL 06/45] target/arm: Convert division from feature bits to isar0 tests, Peter Maydell, 2018/10/19
- [Qemu-devel] [PULL 07/45] target/arm: Convert jazelle from feature bit to isar1 test, Peter Maydell, 2018/10/19
- [Qemu-devel] [PULL 08/45] target/arm: Convert t32ee from feature bit to isar3 test, Peter Maydell, 2018/10/19
- [Qemu-devel] [PULL 09/45] target/arm: Convert sve from feature bit to aa64pfr0 test, Peter Maydell, 2018/10/19
- [Qemu-devel] [PULL 03/45] target/arm: Move some system registers into a substructure, Peter Maydell, 2018/10/19
- [Qemu-devel] [PULL 05/45] target/arm: Convert v8 extensions from feature bits to isar tests, Peter Maydell, 2018/10/19
- [Qemu-devel] [PULL 10/45] target/arm: Convert v8.2-fp16 from feature bit to aa64pfr0 test, Peter Maydell, 2018/10/19
- [Qemu-devel] [PULL 11/45] target/arm: Improve debug logging of AArch32 exception return, Peter Maydell, 2018/10/19
- [Qemu-devel] [PULL 21/45] hw/arm/boot: Increase compliance with kernel arm64 boot protocol, Peter Maydell, 2018/10/19
- [Qemu-devel] [PULL 20/45] target/arm: Report correct syndrome for FP/SIMD traps to Hyp mode, Peter Maydell, 2018/10/19
- [Qemu-devel] [PULL 22/45] target/arm: Hoist address increment for vector memory ops,
Peter Maydell <=
- [Qemu-devel] [PULL 36/45] target/arm: Use gvec for NEON_3R_VML, Peter Maydell, 2018/10/19
- [Qemu-devel] [PULL 35/45] target/arm: Use gvec for VSRI, VSLI, Peter Maydell, 2018/10/19
- [Qemu-devel] [PULL 38/45] target/arm: Use gvec for NEON VLD all lanes, Peter Maydell, 2018/10/19
- [Qemu-devel] [PULL 45/45] target/arm: Only flush tlb if ASID changes, Peter Maydell, 2018/10/19
- [Qemu-devel] [PULL 44/45] target/arm: Remove writefn from TTBR0_EL3, Peter Maydell, 2018/10/19
- [Qemu-devel] [PULL 43/45] net: cadence_gem: Announce 64bit addressing support, Peter Maydell, 2018/10/19
- [Qemu-devel] [PULL 42/45] net: cadence_gem: Announce availability of priority queues, Peter Maydell, 2018/10/19
- [Qemu-devel] [PULL 41/45] target/arm: Reorg NEON VLD/VST single element to one lane, Peter Maydell, 2018/10/19
- [Qemu-devel] [PULL 40/45] target/arm: Promote consecutive memory ops for aa32, Peter Maydell, 2018/10/19
- [Qemu-devel] [PULL 39/45] target/arm: Reorg NEON VLD/VST all elements, Peter Maydell, 2018/10/19