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[Qemu-devel] [PULL 21/45] hw/arm/boot: Increase compliance with kernel a
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 21/45] hw/arm/boot: Increase compliance with kernel arm64 boot protocol |
Date: |
Fri, 19 Oct 2018 17:57:11 +0100 |
From: Stewart Hildebrand <address@hidden>
"The Image must be placed text_offset bytes from a 2MB aligned base
address anywhere in usable system RAM and called there."
For the virt board, we write our startup bootloader at the very
bottom of RAM, so that bit can't be used for the image. To avoid
overlap in case the image requests to be loaded at an offset
smaller than our bootloader, we increment the load offset to the
next 2MB.
This fixes a boot failure for Xen AArch64.
Signed-off-by: Stewart Hildebrand <address@hidden>
Tested-by: Andre Przywara <address@hidden>
Message-id: address@hidden
[PMM: Rephrased a comment a bit]
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
hw/arm/boot.c | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index 20c71d7d961..586baa9b647 100644
--- a/hw/arm/boot.c
+++ b/hw/arm/boot.c
@@ -24,6 +24,7 @@
#include "qemu/config-file.h"
#include "qemu/option.h"
#include "exec/address-spaces.h"
+#include "qemu/units.h"
/* Kernel boot protocol is specified in the kernel docs
* Documentation/arm/Booting and Documentation/arm64/booting.txt
@@ -36,6 +37,8 @@
#define ARM64_TEXT_OFFSET_OFFSET 8
#define ARM64_MAGIC_OFFSET 56
+#define BOOTLOADER_MAX_SIZE (4 * KiB)
+
AddressSpace *arm_boot_address_space(ARMCPU *cpu,
const struct arm_boot_info *info)
{
@@ -184,6 +187,8 @@ static void write_bootloader(const char *name, hwaddr addr,
code[i] = tswap32(insn);
}
+ assert((len * sizeof(uint32_t)) < BOOTLOADER_MAX_SIZE);
+
rom_add_blob_fixed_as(name, code, len * sizeof(uint32_t), addr, as);
g_free(code);
@@ -919,6 +924,19 @@ static uint64_t load_aarch64_image(const char *filename,
hwaddr mem_base,
memcpy(&hdrvals, buffer + ARM64_TEXT_OFFSET_OFFSET, sizeof(hdrvals));
if (hdrvals[1] != 0) {
kernel_load_offset = le64_to_cpu(hdrvals[0]);
+
+ /*
+ * We write our startup "bootloader" at the very bottom of RAM,
+ * so that bit can't be used for the image. Luckily the Image
+ * format specification is that the image requests only an offset
+ * from a 2MB boundary, not an absolute load address. So if the
+ * image requests an offset that might mean it overlaps with the
+ * bootloader, we can just load it starting at 2MB+offset rather
+ * than 0MB + offset.
+ */
+ if (kernel_load_offset < BOOTLOADER_MAX_SIZE) {
+ kernel_load_offset += 2 * MiB;
+ }
}
}
--
2.19.1
- [Qemu-devel] [PULL 02/45] target/arm: Add support for VCPU event states, (continued)
- [Qemu-devel] [PULL 02/45] target/arm: Add support for VCPU event states, Peter Maydell, 2018/10/19
- [Qemu-devel] [PULL 04/45] target/arm: V8M should not imply V7VE, Peter Maydell, 2018/10/19
- [Qemu-devel] [PULL 06/45] target/arm: Convert division from feature bits to isar0 tests, Peter Maydell, 2018/10/19
- [Qemu-devel] [PULL 07/45] target/arm: Convert jazelle from feature bit to isar1 test, Peter Maydell, 2018/10/19
- [Qemu-devel] [PULL 08/45] target/arm: Convert t32ee from feature bit to isar3 test, Peter Maydell, 2018/10/19
- [Qemu-devel] [PULL 09/45] target/arm: Convert sve from feature bit to aa64pfr0 test, Peter Maydell, 2018/10/19
- [Qemu-devel] [PULL 03/45] target/arm: Move some system registers into a substructure, Peter Maydell, 2018/10/19
- [Qemu-devel] [PULL 05/45] target/arm: Convert v8 extensions from feature bits to isar tests, Peter Maydell, 2018/10/19
- [Qemu-devel] [PULL 10/45] target/arm: Convert v8.2-fp16 from feature bit to aa64pfr0 test, Peter Maydell, 2018/10/19
- [Qemu-devel] [PULL 11/45] target/arm: Improve debug logging of AArch32 exception return, Peter Maydell, 2018/10/19
- [Qemu-devel] [PULL 21/45] hw/arm/boot: Increase compliance with kernel arm64 boot protocol,
Peter Maydell <=
- [Qemu-devel] [PULL 20/45] target/arm: Report correct syndrome for FP/SIMD traps to Hyp mode, Peter Maydell, 2018/10/19
- [Qemu-devel] [PULL 22/45] target/arm: Hoist address increment for vector memory ops, Peter Maydell, 2018/10/19
- [Qemu-devel] [PULL 36/45] target/arm: Use gvec for NEON_3R_VML, Peter Maydell, 2018/10/19
- [Qemu-devel] [PULL 35/45] target/arm: Use gvec for VSRI, VSLI, Peter Maydell, 2018/10/19
- [Qemu-devel] [PULL 38/45] target/arm: Use gvec for NEON VLD all lanes, Peter Maydell, 2018/10/19
- [Qemu-devel] [PULL 45/45] target/arm: Only flush tlb if ASID changes, Peter Maydell, 2018/10/19
- [Qemu-devel] [PULL 44/45] target/arm: Remove writefn from TTBR0_EL3, Peter Maydell, 2018/10/19
- [Qemu-devel] [PULL 43/45] net: cadence_gem: Announce 64bit addressing support, Peter Maydell, 2018/10/19
- [Qemu-devel] [PULL 42/45] net: cadence_gem: Announce availability of priority queues, Peter Maydell, 2018/10/19
- [Qemu-devel] [PULL 41/45] target/arm: Reorg NEON VLD/VST single element to one lane, Peter Maydell, 2018/10/19