[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PULL v2 11/33] target/mips: Add a placeholder for R5900 MM
From: |
Aleksandar Markovic |
Subject: |
[Qemu-devel] [PULL v2 11/33] target/mips: Add a placeholder for R5900 MMI instruction class |
Date: |
Wed, 24 Oct 2018 15:40:25 +0200 |
From: Fredrik Noring <address@hidden>
Add a placeholder for MMI class. This is the main palceholder for
MMI ASE.
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Fredrik Noring <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
---
target/mips/translate.c | 45 ++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 44 insertions(+), 1 deletion(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 2318116..6cb6966 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -24420,6 +24420,45 @@ static void decode_opc_special3_legacy(CPUMIPSState
*env, DisasContext *ctx)
}
}
+static void decode_tx79_mmi(CPUMIPSState *env, DisasContext *ctx)
+{
+ uint32_t opc = MASK_TX79_MMI(ctx->opcode);
+
+ switch (opc) {
+ case TX79_MMI_MADD: /* TODO: TX79_MMI_MADD */
+ case TX79_MMI_MADDU: /* TODO: TX79_MMI_MADDU */
+ case TX79_MMI_PLZCW: /* TODO: TX79_MMI_PLZCW */
+ case TX79_MMI_CLASS_MMI0: /* TODO: TX79_MMI_CLASS_MMI0 */
+ case TX79_MMI_CLASS_MMI2: /* TODO: TX79_MMI_CLASS_MMI2 */
+ case TX79_MMI_MFHI1: /* TODO: TX79_MMI_MFHI1 */
+ case TX79_MMI_MTHI1: /* TODO: TX79_MMI_MTHI1 */
+ case TX79_MMI_MFLO1: /* TODO: TX79_MMI_MFLO1 */
+ case TX79_MMI_MTLO1: /* TODO: TX79_MMI_MTLO1 */
+ case TX79_MMI_MULT1: /* TODO: TX79_MMI_MULT1 */
+ case TX79_MMI_MULTU1: /* TODO: TX79_MMI_MULTU1 */
+ case TX79_MMI_DIV1: /* TODO: TX79_MMI_DIV1 */
+ case TX79_MMI_DIVU1: /* TODO: TX79_MMI_DIVU1 */
+ case TX79_MMI_MADD1: /* TODO: TX79_MMI_MADD1 */
+ case TX79_MMI_MADDU1: /* TODO: TX79_MMI_MADDU1 */
+ case TX79_MMI_CLASS_MMI1: /* TODO: TX79_MMI_CLASS_MMI1 */
+ case TX79_MMI_CLASS_MMI3: /* TODO: TX79_MMI_CLASS_MMI3 */
+ case TX79_MMI_PMFHL: /* TODO: TX79_MMI_PMFHL */
+ case TX79_MMI_PMTHL: /* TODO: TX79_MMI_PMTHL */
+ case TX79_MMI_PSLLH: /* TODO: TX79_MMI_PSLLH */
+ case TX79_MMI_PSRLH: /* TODO: TX79_MMI_PSRLH */
+ case TX79_MMI_PSRAH: /* TODO: TX79_MMI_PSRAH */
+ case TX79_MMI_PSLLW: /* TODO: TX79_MMI_PSLLW */
+ case TX79_MMI_PSRLW: /* TODO: TX79_MMI_PSRLW */
+ case TX79_MMI_PSRAW: /* TODO: TX79_MMI_PSRAW */
+ generate_exception_end(ctx, EXCP_RI); /* TODO: TX79_CLASS_MMI */
+ break;
+ default:
+ MIPS_INVAL("TX79 MMI class");
+ generate_exception_end(ctx, EXCP_RI);
+ break;
+ }
+}
+
static void decode_tx79_lq(CPUMIPSState *env, DisasContext *ctx)
{
generate_exception_end(ctx, EXCP_RI); /* TODO: TX79_LQ */
@@ -25769,7 +25808,11 @@ static void decode_opc(CPUMIPSState *env, DisasContext
*ctx)
decode_opc_special(env, ctx);
break;
case OPC_SPECIAL2:
- decode_opc_special2_legacy(env, ctx);
+ if ((ctx->insn_flags & INSN_R5900) && (ctx->insn_flags & ASE_MMI)) {
+ decode_tx79_mmi(env, ctx);
+ } else {
+ decode_opc_special2_legacy(env, ctx);
+ }
break;
case OPC_SPECIAL3:
if (ctx->insn_flags & INSN_R5900) {
--
2.7.4
- [Qemu-devel] [PULL v2 00/33] MIPS queue for October 2018 - part 2 - v2, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 01/33] target/mips: Define R5900 ISA, MMI ASE, and R5900 CPU preprocessor constants, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 02/33] target/mips: Add R5900 Multimedia Instruction overview note, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 13/33] target/mips: Add a placeholder for R5900 MMI1 instruction subclass, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 09/33] target/mips: Add a placeholder for R5900 SQ, handle user mode RDHWR, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 04/33] target/mips: Define R5900 MMI<0|1|2|3> subclasses and opcode constants, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 03/33] target/mips: Define R5900 MMI class, and LQ and SQ opcode constants, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 11/33] target/mips: Add a placeholder for R5900 MMI instruction class,
Aleksandar Markovic <=
- [Qemu-devel] [PULL v2 14/33] target/mips: Add a placeholder for R5900 MMI2 instruction subclass, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 16/33] target/mips: Support R5900 three-operand MULT and MULTU instructions, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 05/33] target/mips: Define R5900 MMI0 opcode constants, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 06/33] target/mips: Define R5900 MMI1 opcode constants, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 12/33] target/mips: Add a placeholder for R5900 MMI0 instruction subclass, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 08/33] target/mips: Define R5900 MMI3 opcode constants, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 20/33] target/mips: Support R5900 MOVN, MOVZ and PREF instructions from MIPS IV, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 29/33] tests/tcg/mips: Add tests for R5900 DIVU1, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 24/33] tests/tcg/mips: Add tests for R5900 three-operand MULT1, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 17/33] target/mips: Support R5900 three-operand MULT1 and MULTU1 instructions, Aleksandar Markovic, 2018/10/24