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[Qemu-devel] [PULL v2 16/33] target/mips: Support R5900 three-operand MU
From: |
Aleksandar Markovic |
Subject: |
[Qemu-devel] [PULL v2 16/33] target/mips: Support R5900 three-operand MULT and MULTU instructions |
Date: |
Wed, 24 Oct 2018 15:40:30 +0200 |
From: Fredrik Noring <address@hidden>
The three-operand MULT and MULTU are the only R5900-specific
instructions emitted by GCC 7.3. The R5900 also implements the three-
operand MADD and MADDU instructions, but they are omitted in QEMU for
now since they are absent in programs compiled by current GCC versions.
Likewise, the R5900-specific pipeline 1 instruction variants MULT1,
MULTU1, DIV1, DIVU1, MADD1, MADDU1, MFHI1, MFLO1, MTHI1 and MTLO1
are omitted here as well.
Reviewed-by: Aleksandar Markovic <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Fredrik Noring <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
---
target/mips/translate.c | 74 +++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 74 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 1c0400c..3dc6d80 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -4766,6 +4766,78 @@ static void gen_muldiv(DisasContext *ctx, uint32_t opc,
tcg_temp_free(t1);
}
+/*
+ * These MULT and MULTU instructions implemented in for example the
+ * Toshiba/Sony R5900 and the Toshiba TX19, TX39 and TX79 core
+ * architectures are special three-operand variants with the syntax
+ *
+ * MULT[U] rd, rs, rt
+ *
+ * such that
+ *
+ * (rd, LO, HI) <- rs * rt
+ *
+ * where the low-order 32-bits of the result is placed into both the
+ * GPR rd and the special register LO. The high-order 32-bits of the
+ * result is placed into the special register HI.
+ *
+ * If the GPR rd is omitted in assembly language, it is taken to be 0,
+ * which is the zero register that always reads as 0.
+ */
+static void gen_mul_txx9(DisasContext *ctx, uint32_t opc,
+ int rd, int rs, int rt)
+{
+ TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
+ int acc = 0;
+
+ gen_load_gpr(t0, rs);
+ gen_load_gpr(t1, rt);
+
+ switch (opc) {
+ case OPC_MULT:
+ {
+ TCGv_i32 t2 = tcg_temp_new_i32();
+ TCGv_i32 t3 = tcg_temp_new_i32();
+ tcg_gen_trunc_tl_i32(t2, t0);
+ tcg_gen_trunc_tl_i32(t3, t1);
+ tcg_gen_muls2_i32(t2, t3, t2, t3);
+ if (rd) {
+ tcg_gen_ext_i32_tl(cpu_gpr[rd], t2);
+ }
+ tcg_gen_ext_i32_tl(cpu_LO[acc], t2);
+ tcg_gen_ext_i32_tl(cpu_HI[acc], t3);
+ tcg_temp_free_i32(t2);
+ tcg_temp_free_i32(t3);
+ }
+ break;
+ case OPC_MULTU:
+ {
+ TCGv_i32 t2 = tcg_temp_new_i32();
+ TCGv_i32 t3 = tcg_temp_new_i32();
+ tcg_gen_trunc_tl_i32(t2, t0);
+ tcg_gen_trunc_tl_i32(t3, t1);
+ tcg_gen_mulu2_i32(t2, t3, t2, t3);
+ if (rd) {
+ tcg_gen_ext_i32_tl(cpu_gpr[rd], t2);
+ }
+ tcg_gen_ext_i32_tl(cpu_LO[acc], t2);
+ tcg_gen_ext_i32_tl(cpu_HI[acc], t3);
+ tcg_temp_free_i32(t2);
+ tcg_temp_free_i32(t3);
+ }
+ break;
+ default:
+ MIPS_INVAL("mul TXx9");
+ generate_exception_end(ctx, EXCP_RI);
+ goto out;
+ }
+
+ out:
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+}
+
static void gen_mul_vr54xx (DisasContext *ctx, uint32_t opc,
int rd, int rs, int rt)
{
@@ -23490,6 +23562,8 @@ static void decode_opc_special_legacy(CPUMIPSState
*env, DisasContext *ctx)
check_insn(ctx, INSN_VR54XX);
op1 = MASK_MUL_VR54XX(ctx->opcode);
gen_mul_vr54xx(ctx, op1, rd, rs, rt);
+ } else if (ctx->insn_flags & INSN_R5900) {
+ gen_mul_txx9(ctx, op1, rd, rs, rt);
} else {
gen_muldiv(ctx, op1, rd & 3, rs, rt);
}
--
2.7.4
- [Qemu-devel] [PULL v2 00/33] MIPS queue for October 2018 - part 2 - v2, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 01/33] target/mips: Define R5900 ISA, MMI ASE, and R5900 CPU preprocessor constants, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 02/33] target/mips: Add R5900 Multimedia Instruction overview note, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 13/33] target/mips: Add a placeholder for R5900 MMI1 instruction subclass, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 09/33] target/mips: Add a placeholder for R5900 SQ, handle user mode RDHWR, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 04/33] target/mips: Define R5900 MMI<0|1|2|3> subclasses and opcode constants, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 03/33] target/mips: Define R5900 MMI class, and LQ and SQ opcode constants, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 11/33] target/mips: Add a placeholder for R5900 MMI instruction class, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 14/33] target/mips: Add a placeholder for R5900 MMI2 instruction subclass, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 16/33] target/mips: Support R5900 three-operand MULT and MULTU instructions,
Aleksandar Markovic <=
- [Qemu-devel] [PULL v2 05/33] target/mips: Define R5900 MMI0 opcode constants, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 06/33] target/mips: Define R5900 MMI1 opcode constants, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 12/33] target/mips: Add a placeholder for R5900 MMI0 instruction subclass, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 08/33] target/mips: Define R5900 MMI3 opcode constants, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 20/33] target/mips: Support R5900 MOVN, MOVZ and PREF instructions from MIPS IV, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 29/33] tests/tcg/mips: Add tests for R5900 DIVU1, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 24/33] tests/tcg/mips: Add tests for R5900 three-operand MULT1, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 17/33] target/mips: Support R5900 three-operand MULT1 and MULTU1 instructions, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 23/33] tests/tcg/mips: Add tests for R5900 three-operand MULTU, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 18/33] target/mips: Support R5900 MFLO1, MTLO1, MFHI1 and MTHI1 instructions, Aleksandar Markovic, 2018/10/24