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[Qemu-devel] [PULL v2 29/33] tests/tcg/mips: Add tests for R5900 DIVU1
From: |
Aleksandar Markovic |
Subject: |
[Qemu-devel] [PULL v2 29/33] tests/tcg/mips: Add tests for R5900 DIVU1 |
Date: |
Wed, 24 Oct 2018 15:40:43 +0200 |
From: Fredrik Noring <address@hidden>
Add a test for DIVU1.
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Fredrik Noring <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
---
tests/tcg/mips/mipsr5900/Makefile | 1 +
tests/tcg/mips/mipsr5900/divu1.c | 48 +++++++++++++++++++++++++++++++++++++++
2 files changed, 49 insertions(+)
create mode 100644 tests/tcg/mips/mipsr5900/divu1.c
diff --git a/tests/tcg/mips/mipsr5900/Makefile
b/tests/tcg/mips/mipsr5900/Makefile
index 757eb83..a1c388b 100644
--- a/tests/tcg/mips/mipsr5900/Makefile
+++ b/tests/tcg/mips/mipsr5900/Makefile
@@ -9,6 +9,7 @@ CC = $(CROSS)gcc
CFLAGS = -Wall -mabi=32 -march=r5900 -static
TESTCASES = div1.tst
+TESTCASES += divu1.tst
TESTCASES += mflohi1.tst
TESTCASES += mtlohi1.tst
TESTCASES += mult.tst
diff --git a/tests/tcg/mips/mipsr5900/divu1.c b/tests/tcg/mips/mipsr5900/divu1.c
new file mode 100644
index 0000000..72aeed3
--- /dev/null
+++ b/tests/tcg/mips/mipsr5900/divu1.c
@@ -0,0 +1,48 @@
+/*
+ * Test R5900-specific DIVU1.
+ */
+
+#include <stdio.h>
+#include <inttypes.h>
+#include <assert.h>
+
+struct quotient_remainder { uint32_t quotient, remainder; };
+
+static struct quotient_remainder divu1(uint32_t rs, uint32_t rt)
+{
+ uint32_t lo, hi;
+
+ __asm__ __volatile__ (
+ " divu1 $0, %2, %3\n"
+ " mflo1 %0\n"
+ " mfhi1 %1\n"
+ : "=r" (lo), "=r" (hi)
+ : "r" (rs), "r" (rt));
+
+ assert(rs / rt == lo);
+ assert(rs % rt == hi);
+
+ return (struct quotient_remainder) { .quotient = lo, .remainder = hi };
+}
+
+static void verify_divu1(uint32_t rs, uint32_t rt,
+ uint32_t expected_quotient,
+ uint32_t expected_remainder)
+{
+ struct quotient_remainder qr = divu1(rs, rt);
+
+ assert(qr.quotient == expected_quotient);
+ assert(qr.remainder == expected_remainder);
+}
+
+int main()
+{
+ verify_divu1(0, 1, 0, 0);
+ verify_divu1(1, 1, 1, 0);
+ verify_divu1(1, 2, 0, 1);
+ verify_divu1(17, 19, 0, 17);
+ verify_divu1(19, 17, 1, 2);
+ verify_divu1(77773, 101, 770, 3);
+
+ return 0;
+}
--
2.7.4
- [Qemu-devel] [PULL v2 04/33] target/mips: Define R5900 MMI<0|1|2|3> subclasses and opcode constants, (continued)
- [Qemu-devel] [PULL v2 04/33] target/mips: Define R5900 MMI<0|1|2|3> subclasses and opcode constants, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 03/33] target/mips: Define R5900 MMI class, and LQ and SQ opcode constants, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 11/33] target/mips: Add a placeholder for R5900 MMI instruction class, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 14/33] target/mips: Add a placeholder for R5900 MMI2 instruction subclass, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 16/33] target/mips: Support R5900 three-operand MULT and MULTU instructions, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 05/33] target/mips: Define R5900 MMI0 opcode constants, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 06/33] target/mips: Define R5900 MMI1 opcode constants, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 12/33] target/mips: Add a placeholder for R5900 MMI0 instruction subclass, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 08/33] target/mips: Define R5900 MMI3 opcode constants, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 20/33] target/mips: Support R5900 MOVN, MOVZ and PREF instructions from MIPS IV, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 29/33] tests/tcg/mips: Add tests for R5900 DIVU1,
Aleksandar Markovic <=
- [Qemu-devel] [PULL v2 24/33] tests/tcg/mips: Add tests for R5900 three-operand MULT1, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 17/33] target/mips: Support R5900 three-operand MULT1 and MULTU1 instructions, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 23/33] tests/tcg/mips: Add tests for R5900 three-operand MULTU, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 18/33] target/mips: Support R5900 MFLO1, MTLO1, MFHI1 and MTHI1 instructions, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 30/33] target/mips: Define the R5900 CPU, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 26/33] tests/tcg/mips: Add tests for R5900 MFLO1 and MFHI1, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 22/33] tests/tcg/mips: Add tests for R5900 three-operand MULT, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 25/33] tests/tcg/mips: Add tests for R5900 three-operand MULTU1, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 21/33] target/mips: Make R5900 DMULT[U], DDIV[U], LL[D] and SC[D] user only, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 15/33] target/mips: Add a placeholder for R5900 MMI3 instruction subclass, Aleksandar Markovic, 2018/10/24