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[Qemu-ppc] [PATCH RFC v0 4/6] target-ppc: add vslv instruction
From: |
Nikunj A Dadhania |
Subject: |
[Qemu-ppc] [PATCH RFC v0 4/6] target-ppc: add vslv instruction |
Date: |
Wed, 27 Jul 2016 00:56:56 +0530 |
From: Vivek Andrew Sha <address@hidden>
vslv: Vector Shift Left Variable
Signed-off-by: Vivek Andrew Sha <address@hidden>
Signed-off-by: Nikunj A Dadhania <address@hidden>
---
target-ppc/helper.h | 1 +
target-ppc/int_helper.c | 14 ++++++++++++++
target-ppc/translate.c | 2 ++
3 files changed, 17 insertions(+)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index e93b84b..9703f85 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -211,6 +211,7 @@ DEF_HELPER_3(vslw, void, avr, avr, avr)
DEF_HELPER_3(vsld, void, avr, avr, avr)
DEF_HELPER_3(vslo, void, avr, avr, avr)
DEF_HELPER_3(vsro, void, avr, avr, avr)
+DEF_HELPER_3(vslv, void, avr, avr, avr)
DEF_HELPER_3(vaddcuw, void, avr, avr, avr)
DEF_HELPER_3(vsubcuw, void, avr, avr, avr)
DEF_HELPER_2(lvsl, void, avr, tl)
diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
index bffe8d6..412398f 100644
--- a/target-ppc/int_helper.c
+++ b/target-ppc/int_helper.c
@@ -1708,6 +1708,20 @@ VSL(w, u32, 0x1F)
VSL(d, u64, 0x3F)
#undef VSL
+void helper_vslv(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
+{
+ int i;
+ unsigned int shift, bytes, size;
+
+ size = ARRAY_SIZE(r->u8);
+ for (i = 0; i < size; i++) {
+ shift = b->u8[i] & 0x7; /* extract shift value */
+ bytes = (a->u8[i] << 8) + /* extract adjacent bytes */
+ (((i + 1) < size) ? a->u8[i + 1] : 0);
+ r->u8[i] = (bytes << shift) >> 8; /* shift and store result */
+ }
+}
+
void helper_vsldoi(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t shift)
{
int sh = shift & 0xf;
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 7cf0c8e..473f21a 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7457,6 +7457,7 @@ GEN_VXFORM(vsraw, 2, 14);
GEN_VXFORM(vsrad, 2, 15);
GEN_VXFORM(vslo, 6, 16);
GEN_VXFORM(vsro, 6, 17);
+GEN_VXFORM(vslv, 2, 29);
GEN_VXFORM(vaddcuw, 0, 6);
GEN_VXFORM(vsubcuw, 0, 22);
GEN_VXFORM_ENV(vaddubs, 0, 8);
@@ -10942,6 +10943,7 @@ GEN_VXFORM(vsraw, 2, 14),
GEN_VXFORM_207(vsrad, 2, 15),
GEN_VXFORM(vslo, 6, 16),
GEN_VXFORM(vsro, 6, 17),
+GEN_VXFORM(vslv, 2, 29),
GEN_VXFORM(vaddcuw, 0, 6),
GEN_VXFORM(vsubcuw, 0, 22),
GEN_VXFORM(vaddubs, 0, 8),
--
2.7.4
- [Qemu-ppc] [PATCH RFC v0 0/6] POWER9 TCG enablements - part2, Nikunj A Dadhania, 2016/07/26
- [Qemu-ppc] [PATCH RFC v0 1/6] target-ppc: add dtstsfi[q] instructions, Nikunj A Dadhania, 2016/07/26
- [Qemu-ppc] [PATCH RFC v0 2/6] target-ppc: add vabsdu[b, h, w] instructions, Nikunj A Dadhania, 2016/07/26
- [Qemu-ppc] [PATCH RFC v0 3/6] target-ppc: add vcmpnez[b, h, w][.] instructions, Nikunj A Dadhania, 2016/07/26
- [Qemu-ppc] [PATCH RFC v0 4/6] target-ppc: add vslv instruction,
Nikunj A Dadhania <=
- [Qemu-ppc] [PATCH RFC v0 5/6] target-ppc: add vsrv instruction, Nikunj A Dadhania, 2016/07/26
[Qemu-ppc] [PATCH RFC v0 6/6] target-ppc: add extswsli[.] instruction, Nikunj A Dadhania, 2016/07/26
Re: [Qemu-ppc] [PATCH RFC v0 0/6] POWER9 TCG enablements - part2, David Gibson, 2016/07/28