Re: [Simulavr-devel] version control systems

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Re: [Simulavr-devel] version control systems

From:	address@hidden
Subject:	Re: [Simulavr-devel] version control systems
Date:	Sun, 10 Jan 2010 16:10:34 -0700

On Sun Jan  3 12:55 , "address@hidden"  sent:

>On Wed Dec 29  6:05 , ThomasK  sent:
>
>>> Fedora 11 seems not to believe in cvs2git.
>>> I've not been able to find the magic words to make git itself
>>> convert both simulavr and simulavrxx.
>>
>>The magic word, resp. command should be "git help cvsimport", my 
>
>It's what I started with.
>I think I'm making progress, but I'm not there yet.
>Remember I'm pretty much starting from scratch.
>I don't yet even have a mental model of what git manipulates.

I was wrong.
I'm not making progress.
I've attached my latest effort.

I'm not sure I'll want to use git even if it is the greatest
thing since bread and even if I manage to figure it out.
I can never be sure I'm doing anything right.
The prospect of typing every command with fear and trepidation does not appeal.

---
Michael Hennebry
address@hidden
"War is only a hobby."
---- Msg sent via CableONE.net MyMail - http://www.cableone.net

Script started on Sun 10 Jan 2010 04:50:24 PM CST
]0;address@hidden:~/projects/avr/address@hidden sim]$ git cvsimport -C 
git_from_cvs -d $PWD/cvsrep091010
Initialized empty Git repository in 
/home/hennebry/projects/avr/sim/git_from_cvs/.git/
Unknown: error  
]0;address@hidden:~/projects/avr/address@hidden sim]$ ls -r[Ka .,[K 
git_from_cvs
.:
./                   cvs0708/                mypy/
../                  cvs0708p/               net.txt
b0605/               cvs0708up/              pysimulavr/
b0605-old/           cvs0708up.iso           pysimulavr.tar.gz
b0708a/              cvs0709/                PyTutorial98.pdf
b0708upnop/          cvs0710/                simulavrxx/
b0708upnop-old/      cvs2svn-options.txt     simulavrxx_doc.patch
b0708upp/            cvs-co                  simulavrxx.info
b0709a/              cvsrep091010/           simulavrxx.texinfo
b0710/               damn.txt                std12.txt
bases.txt            decoder_bases.txt       SWIGMaster.pdf
.bases.txt.swp       flow.txt                swigmaster.zip
bcp0710/             fred/                   symbol-info.txt
bootstrap.0709.txt   fred.txt                target/
brett.tar.gz         from_cvs/               timer_regs.txt
cnotes.txt           git-cvsimport.txt       trunk/
config.h             .git-cvsimport.txt.swp  unwrap.py
configure--help.txt  git_from_cvs/           versioning.txt
cp0710/              HWMegaTimer0.txt        work/
CVS/                 Makefile

git_from_cvs:
./  ../  .git/
]0;address@hidden:~/projects/avr/address@hidden sim]$ cvs chech[Kkout 
-d[K[K[K[K[K[K[K[K[K[K[K-d  $PWD/cvsrep091010 -d greg .
Unknown command: `.'

CVS commands are:
        add          Add a new file/directory to the repository
        admin        Administration front end for rcs
        annotate     Show last revision where each line was modified
        checkout     Checkout sources for editing
        commit       Check files into the repository
        diff         Show differences between revisions
        edit         Get ready to edit a watched file
        editors      See who is editing a watched file
        export       Export sources from CVS, similar to checkout
        history      Show repository access history
        import       Import sources into CVS, using vendor branches
        init         Create a CVS repository if it doesn't exist
        log          Print out history information for files
        login        Prompt for password for authenticating server
        logout       Removes entry in .cvspass for remote repository
        pserver      Password server mode
        rannotate    Show last revision where each line of module was modified
        rdiff        Create 'patch' format diffs between releases
        release      Indicate that a Module is no longer in use
        remove       Remove an entry from the repository
        rlog         Print out history information for a module
        rtag         Add a symbolic tag to a module
        server       Server mode
        status       Display status information on checked out files
        tag          Add a symbolic tag to checked out version of files
        unedit       Undo an edit command
        update       Bring work tree in sync with repository
        version      Show current CVS version(s)
        watch        Set watches
        watchers     See who is watching a file
(Specify the --help option for a list of other help options)
]0;address@hidden:~/projects/avr/address@hidden sim]$ cvs -d  
$PWD/cvsrep091010 -d greg 
address@hidden@address@hidden@address@hidden@address@hidden@t[1@ 
cvs checkout: Updating greg
cvs checkout: Updating greg/CVSROOT
cvs checkout: Updating greg/simulavr
U greg/simulavr/AUTHORS
U greg/simulavr/COPYING
U greg/simulavr/ChangeLog
U greg/simulavr/ChangeLog-2001
U greg/simulavr/ChangeLog-2002
U greg/simulavr/ChangeLog-2003
U greg/simulavr/INSTALL
U greg/simulavr/Makefile.am
U greg/simulavr/Makefile_AVR_Rules
U greg/simulavr/ProjSummary
U greg/simulavr/README
U greg/simulavr/README.cygwin
U greg/simulavr/README.ext_int
U greg/simulavr/README.gdb
U greg/simulavr/README.mem_vdev
U greg/simulavr/README.opcodes
U greg/simulavr/TODO
U greg/simulavr/bootstrap
U greg/simulavr/configure.ac
U greg/simulavr/simulavr-disp.1.in
U greg/simulavr/simulavr.1.in
U greg/simulavr/simulavr.spec.in
cvs checkout: Updating greg/simulavr/avr
cvs checkout: Updating greg/simulavr/config
cvs checkout: Updating greg/simulavr/dev
cvs checkout: Updating greg/simulavr/doc
U greg/simulavr/doc/Makefile.am
U greg/simulavr/doc/dox.css
U greg/simulavr/doc/dox_html_footer
U greg/simulavr/doc/dox_html_header
U greg/simulavr/doc/doxygen.config.in
U greg/simulavr/doc/main.dox
U greg/simulavr/doc/simulavr.texi
U greg/simulavr/doc/texinfo.tex
cvs checkout: Updating greg/simulavr/gdb-patches
cvs checkout: Updating greg/simulavr/misc
U greg/simulavr/misc/defn_tmpl_h
U greg/simulavr/misc/gpl_header
U greg/simulavr/misc/gpl_header_c
U greg/simulavr/misc/gpl_header_h
U greg/simulavr/misc/gpl_header_py
U greg/simulavr/misc/io_gen.py
U greg/simulavr/misc/irq.py
U greg/simulavr/misc/refmt.sh
cvs checkout: Updating greg/simulavr/python
cvs checkout: Updating greg/simulavr/python/avr
cvs checkout: Updating greg/simulavr/python/dev
cvs checkout: Updating greg/simulavr/regress
U greg/simulavr/regress/Makefile.am
U greg/simulavr/regress/README
U greg/simulavr/regress/regress.py.in
cvs checkout: Updating greg/simulavr/regress/modules
U greg/simulavr/regress/modules/.cvsignore
U greg/simulavr/regress/modules/Makefile.am
U greg/simulavr/regress/modules/avr_target.py
U greg/simulavr/regress/modules/base_test.py
U greg/simulavr/regress/modules/gdb_rsp.py
U greg/simulavr/regress/modules/registers.py
cvs checkout: Updating greg/simulavr/regress/test_opcodes
U greg/simulavr/regress/test_opcodes/.cvsignore
U greg/simulavr/regress/test_opcodes/Makefile.am
U greg/simulavr/regress/test_opcodes/TODO
U greg/simulavr/regress/test_opcodes/test_ADC.py
U greg/simulavr/regress/test_opcodes/test_ADD.py
U greg/simulavr/regress/test_opcodes/test_ADIW.py
U greg/simulavr/regress/test_opcodes/test_AND.py
U greg/simulavr/regress/test_opcodes/test_ANDI.py
U greg/simulavr/regress/test_opcodes/test_ASR.py
U greg/simulavr/regress/test_opcodes/test_BCLR.py
U greg/simulavr/regress/test_opcodes/test_BLD.py
U greg/simulavr/regress/test_opcodes/test_BRBC.py
U greg/simulavr/regress/test_opcodes/test_BRBS.py
U greg/simulavr/regress/test_opcodes/test_BSET.py
U greg/simulavr/regress/test_opcodes/test_BST.py
U greg/simulavr/regress/test_opcodes/test_CALL.py
U greg/simulavr/regress/test_opcodes/test_COM.py
U greg/simulavr/regress/test_opcodes/test_CP.py
U greg/simulavr/regress/test_opcodes/test_CPC.py
U greg/simulavr/regress/test_opcodes/test_CPI.py
U greg/simulavr/regress/test_opcodes/test_CPSE.py
U greg/simulavr/regress/test_opcodes/test_DEC.py
U greg/simulavr/regress/test_opcodes/test_EOR.py
U greg/simulavr/regress/test_opcodes/test_ICALL.py
U greg/simulavr/regress/test_opcodes/test_IJMP.py
U greg/simulavr/regress/test_opcodes/test_INC.py
U greg/simulavr/regress/test_opcodes/test_JMP.py
U greg/simulavr/regress/test_opcodes/test_LDD_Y.py
U greg/simulavr/regress/test_opcodes/test_LDD_Z.py
U greg/simulavr/regress/test_opcodes/test_LDI.py
U greg/simulavr/regress/test_opcodes/test_LDS.py
U greg/simulavr/regress/test_opcodes/test_LD_X.py
U greg/simulavr/regress/test_opcodes/test_LD_X_decr.py
U greg/simulavr/regress/test_opcodes/test_LD_X_incr.py
U greg/simulavr/regress/test_opcodes/test_LD_Y_decr.py
U greg/simulavr/regress/test_opcodes/test_LD_Y_incr.py
U greg/simulavr/regress/test_opcodes/test_LD_Z_decr.py
U greg/simulavr/regress/test_opcodes/test_LD_Z_incr.py
U greg/simulavr/regress/test_opcodes/test_LPM.py
U greg/simulavr/regress/test_opcodes/test_LPM_Z.py
U greg/simulavr/regress/test_opcodes/test_LPM_Z_incr.py
U greg/simulavr/regress/test_opcodes/test_LSR.py
U greg/simulavr/regress/test_opcodes/test_MOV.py
U greg/simulavr/regress/test_opcodes/test_MOVW.py
U greg/simulavr/regress/test_opcodes/test_MUL.py
U greg/simulavr/regress/test_opcodes/test_MULS.py
U greg/simulavr/regress/test_opcodes/test_MULSU.py
U greg/simulavr/regress/test_opcodes/test_NEG.py
U greg/simulavr/regress/test_opcodes/test_NOP.py
U greg/simulavr/regress/test_opcodes/test_OR.py
U greg/simulavr/regress/test_opcodes/test_ORI.py
U greg/simulavr/regress/test_opcodes/test_POP.py
U greg/simulavr/regress/test_opcodes/test_PUSH.py
U greg/simulavr/regress/test_opcodes/test_RCALL.py
U greg/simulavr/regress/test_opcodes/test_RET.py
U greg/simulavr/regress/test_opcodes/test_RETI.py
U greg/simulavr/regress/test_opcodes/test_RJMP.py
U greg/simulavr/regress/test_opcodes/test_ROR.py
U greg/simulavr/regress/test_opcodes/test_SBC.py
U greg/simulavr/regress/test_opcodes/test_SBCI.py
U greg/simulavr/regress/test_opcodes/test_SBIW.py
U greg/simulavr/regress/test_opcodes/test_SBRC.py
U greg/simulavr/regress/test_opcodes/test_SBRS.py
U greg/simulavr/regress/test_opcodes/test_STD_Y.py
U greg/simulavr/regress/test_opcodes/test_STD_Z.py
U greg/simulavr/regress/test_opcodes/test_STS.py
U greg/simulavr/regress/test_opcodes/test_ST_X.py
U greg/simulavr/regress/test_opcodes/test_ST_X_decr.py
U greg/simulavr/regress/test_opcodes/test_ST_X_incr.py
U greg/simulavr/regress/test_opcodes/test_ST_Y_decr.py
U greg/simulavr/regress/test_opcodes/test_ST_Y_incr.py
U greg/simulavr/regress/test_opcodes/test_ST_Z_decr.py
U greg/simulavr/regress/test_opcodes/test_ST_Z_incr.py
U greg/simulavr/regress/test_opcodes/test_SUB.py
U greg/simulavr/regress/test_opcodes/test_SUBI.py
U greg/simulavr/regress/test_opcodes/test_SWAP.py
cvs checkout: Updating greg/simulavr/src
U greg/simulavr/src/Makefile.am
U greg/simulavr/src/adc.c
U greg/simulavr/src/adc.h
U greg/simulavr/src/avrclass.c
U greg/simulavr/src/avrclass.h
U greg/simulavr/src/avrcore.c
U greg/simulavr/src/avrcore.h
U greg/simulavr/src/avrerror.c
U greg/simulavr/src/avrerror.h
U greg/simulavr/src/avrmalloc.c
U greg/simulavr/src/avrmalloc.h
U greg/simulavr/src/callback.c
U greg/simulavr/src/callback.h
U greg/simulavr/src/decoder.c
U greg/simulavr/src/decoder.h
U greg/simulavr/src/device.c
U greg/simulavr/src/devsupp.c
U greg/simulavr/src/devsupp.h
U greg/simulavr/src/display.c
U greg/simulavr/src/display.h
U greg/simulavr/src/eeprom.c
U greg/simulavr/src/eeprom.h
U greg/simulavr/src/flash.c
U greg/simulavr/src/flash.h
U greg/simulavr/src/gdb.h
U greg/simulavr/src/gdbserver.c
U greg/simulavr/src/intvects.c
U greg/simulavr/src/intvects.h
U greg/simulavr/src/main.c
U greg/simulavr/src/memory.c
U greg/simulavr/src/memory.h
U greg/simulavr/src/op_names.c
U greg/simulavr/src/op_names.h
U greg/simulavr/src/ports.c
U greg/simulavr/src/ports.h
U greg/simulavr/src/register.c
U greg/simulavr/src/register.h
U greg/simulavr/src/sig.c
U greg/simulavr/src/sig.h
U greg/simulavr/src/spi.c
U greg/simulavr/src/spi.h
U greg/simulavr/src/sram.c
U greg/simulavr/src/sram.h
U greg/simulavr/src/stack.c
U greg/simulavr/src/stack.h
U greg/simulavr/src/storage.c
U greg/simulavr/src/storage.h
U greg/simulavr/src/timers.c
U greg/simulavr/src/timers.h
U greg/simulavr/src/uart.c
U greg/simulavr/src/uart.h
U greg/simulavr/src/usb.c
U greg/simulavr/src/usb.h
U greg/simulavr/src/utils.c
U greg/simulavr/src/utils.h
U greg/simulavr/src/vdevs.h
cvs checkout: Updating greg/simulavr/src/defn
U greg/simulavr/src/defn/43usb320.h
U greg/simulavr/src/defn/43usb325.h
U greg/simulavr/src/defn/43usb326.h
U greg/simulavr/src/defn/43usb351.h
U greg/simulavr/src/defn/43usb353.h
U greg/simulavr/src/defn/43usb355.h
U greg/simulavr/src/defn/90s1200.h
U greg/simulavr/src/defn/90s2313.h
U greg/simulavr/src/defn/90s4414.h
U greg/simulavr/src/defn/90s8515.h
U greg/simulavr/src/defn/mega103.h
U greg/simulavr/src/defn/mega128.h
U greg/simulavr/src/defn/mega16.h
U greg/simulavr/src/defn/mega32.h
U greg/simulavr/src/defn/mega8.h
cvs checkout: Updating greg/simulavr/src/disp
U greg/simulavr/src/disp/Makefile.am
U greg/simulavr/src/disp/disp.c
cvs checkout: Updating greg/simulavr/src/disp-vcd
U greg/simulavr/src/disp-vcd/Makefile.am
U greg/simulavr/src/disp-vcd/config_parser.y
U greg/simulavr/src/disp-vcd/config_scanner.l
U greg/simulavr/src/disp-vcd/disp.c
U greg/simulavr/src/disp-vcd/vcd.c
U greg/simulavr/src/disp-vcd/vcd.cfg
U greg/simulavr/src/disp-vcd/vcd.h
cvs checkout: Updating greg/simulavr/src/getopt
U greg/simulavr/src/getopt/Makefile.am
U greg/simulavr/src/getopt/gnu_getopt.c
U greg/simulavr/src/getopt/gnu_getopt.h
U greg/simulavr/src/getopt/gnu_getopt1.c
cvs checkout: Updating greg/simulavr/test_asm
U greg/simulavr/test_asm/Makefile.am
cvs checkout: Updating greg/simulavr/test_asm/test_8515
U greg/simulavr/test_asm/test_8515/8515def.inc
U greg/simulavr/test_asm/test_8515/Makefile.am
U greg/simulavr/test_asm/test_8515/test_blink.asm
U greg/simulavr/test_asm/test_8515/test_cntr.asm
U greg/simulavr/test_asm/test_8515/test_eeprom.asm
U greg/simulavr/test_asm/test_8515/test_port.asm
U greg/simulavr/test_asm/test_8515/test_stack.asm
U greg/simulavr/test_asm/test_8515/test_toie0.asm
U greg/simulavr/test_asm/test_8515/test_toie0_2.asm
U greg/simulavr/test_asm/test_8515/test_wdr.asm
U greg/simulavr/test_asm/test_8515/test_wdr2.asm
cvs checkout: Updating greg/simulavr/test_c
U greg/simulavr/test_c/Makefile.am
U greg/simulavr/test_c/big_str.h
U greg/simulavr/test_c/common.h
U greg/simulavr/test_c/deep_frame.c
U greg/simulavr/test_c/demo.c
U greg/simulavr/test_c/demo_kr.c
U greg/simulavr/test_c/timer.c
cvs checkout: Updating greg/simulavrxx
U greg/simulavrxx/.cvsignore
U greg/simulavrxx/AUTHORS
U greg/simulavrxx/COPYING
U greg/simulavrxx/ChangeLog
U greg/simulavrxx/INSTALL
U greg/simulavrxx/Makefile.am
U greg/simulavrxx/NEWS
U greg/simulavrxx/README
U greg/simulavrxx/README.gdb
U greg/simulavrxx/SUPPORT
U greg/simulavrxx/TODO
U greg/simulavrxx/bootstrap
U greg/simulavrxx/configure.ac
U greg/simulavrxx/make_tarball
cvs checkout: Updating greg/simulavrxx/autom4te.cache
cvs checkout: Updating greg/simulavrxx/config
cvs checkout: Updating greg/simulavrxx/doc
U greg/simulavrxx/doc/.cvsignore
U greg/simulavrxx/doc/Makefile.am
U greg/simulavrxx/doc/config.texi.in
U greg/simulavrxx/doc/mdate-sh
U greg/simulavrxx/doc/simulavr.texinfo
U greg/simulavrxx/doc/texinfo.tex
U greg/simulavrxx/doc/version.texi
cvs checkout: Updating greg/simulavrxx/examples
U greg/simulavrxx/examples/.cvsignore
U greg/simulavrxx/examples/ChangeLog
U greg/simulavrxx/examples/Makefile.am
U greg/simulavrxx/examples/gui.tcl.in
U greg/simulavrxx/examples/kbd.xbm
U greg/simulavrxx/examples/simulavr.tcl.in
cvs checkout: Updating greg/simulavrxx/examples/anacomp
U greg/simulavrxx/examples/anacomp/.cvsignore
U greg/simulavrxx/examples/anacomp/Makefile.am
U greg/simulavrxx/examples/anacomp/README
U greg/simulavrxx/examples/anacomp/anacomp.tcl
U greg/simulavrxx/examples/anacomp/checkdebug.py
U greg/simulavrxx/examples/anacomp/main.c
cvs checkout: Updating greg/simulavrxx/examples/atmega128_timer
U greg/simulavrxx/examples/atmega128_timer/.cvsignore
U greg/simulavrxx/examples/atmega128_timer/Makefile.am
U greg/simulavrxx/examples/atmega128_timer/README
U greg/simulavrxx/examples/atmega128_timer/debugio.c
U greg/simulavrxx/examples/atmega128_timer/debugio.h
U greg/simulavrxx/examples/atmega128_timer/main.c
cvs checkout: Updating greg/simulavrxx/examples/atmega48
U greg/simulavrxx/examples/atmega48/.cvsignore
U greg/simulavrxx/examples/atmega48/Makefile.am
U greg/simulavrxx/examples/atmega48/Makefile.notauto
U greg/simulavrxx/examples/atmega48/README
U greg/simulavrxx/examples/atmega48/anadata1
U greg/simulavrxx/examples/atmega48/anadata2
U greg/simulavrxx/examples/atmega48/anadata3
U greg/simulavrxx/examples/atmega48/atmega48.tcl
U greg/simulavrxx/examples/atmega48/check.tcl.in
U greg/simulavrxx/examples/atmega48/main.cpp
U greg/simulavrxx/examples/atmega48/spidata
cvs checkout: Updating greg/simulavrxx/examples/atmel_key
U greg/simulavrxx/examples/atmel_key/.cvsignore
U greg/simulavrxx/examples/atmel_key/Makefile.am
U greg/simulavrxx/examples/atmel_key/Notes.txt
U greg/simulavrxx/examples/atmel_key/README
U greg/simulavrxx/examples/atmel_key/StdDefs.c
U greg/simulavrxx/examples/atmel_key/StdDefs.h
U greg/simulavrxx/examples/atmel_key/atmel_key.tcl
U greg/simulavrxx/examples/atmel_key/kb.c
U greg/simulavrxx/examples/atmel_key/kb.h
U greg/simulavrxx/examples/atmel_key/main.c
U greg/simulavrxx/examples/atmel_key/pindefs.h
U greg/simulavrxx/examples/atmel_key/scancodes.h
U greg/simulavrxx/examples/atmel_key/serial.c
U greg/simulavrxx/examples/atmel_key/serial.h
cvs checkout: Updating greg/simulavrxx/examples/feedback
U greg/simulavrxx/examples/feedback/.cvsignore
U greg/simulavrxx/examples/feedback/Makefile.am
U greg/simulavrxx/examples/feedback/README
U greg/simulavrxx/examples/feedback/adc.c
U greg/simulavrxx/examples/feedback/debugio.c
U greg/simulavrxx/examples/feedback/debugio.h
U greg/simulavrxx/examples/feedback/defines.h
U greg/simulavrxx/examples/feedback/feedback.tcl
U greg/simulavrxx/examples/feedback/main.c
U greg/simulavrxx/examples/feedback/simfeedback.tcl.in
U greg/simulavrxx/examples/feedback/uart.c
U greg/simulavrxx/examples/feedback/uart.h
cvs checkout: Updating greg/simulavrxx/examples/simple_ex1
U greg/simulavrxx/examples/simple_ex1/.cvsignore
U greg/simulavrxx/examples/simple_ex1/Makefile.am
U greg/simulavrxx/examples/simple_ex1/fred.c
cvs checkout: Updating greg/simulavrxx/examples/spi
U greg/simulavrxx/examples/spi/.cvsignore
U greg/simulavrxx/examples/spi/Makefile.am
U greg/simulavrxx/examples/spi/Makefile.notauto
U greg/simulavrxx/examples/spi/README
U greg/simulavrxx/examples/spi/anadata
U greg/simulavrxx/examples/spi/check.tcl.in
U greg/simulavrxx/examples/spi/main.cpp
U greg/simulavrxx/examples/spi/spi.tcl
U greg/simulavrxx/examples/spi/spidata
cvs checkout: Updating greg/simulavrxx/examples/stdiodemo
U greg/simulavrxx/examples/stdiodemo/.cvsignore
U greg/simulavrxx/examples/stdiodemo/Makefile.am
U greg/simulavrxx/examples/stdiodemo/README
U greg/simulavrxx/examples/stdiodemo/checkdebug.gdb
U greg/simulavrxx/examples/stdiodemo/checkdebug.tcl.in
U greg/simulavrxx/examples/stdiodemo/defines.h
U greg/simulavrxx/examples/stdiodemo/hd44780.c
U greg/simulavrxx/examples/stdiodemo/hd44780.h
U greg/simulavrxx/examples/stdiodemo/lcd.c
U greg/simulavrxx/examples/stdiodemo/lcd.h
U greg/simulavrxx/examples/stdiodemo/stdiodemo-setup.jpg
U greg/simulavrxx/examples/stdiodemo/stdiodemo.c
U greg/simulavrxx/examples/stdiodemo/stdiodemo.dox
U greg/simulavrxx/examples/stdiodemo/stdiodemo.tcl
U greg/simulavrxx/examples/stdiodemo/uart.c
U greg/simulavrxx/examples/stdiodemo/uart.h
cvs checkout: Updating greg/simulavrxx/m4
U greg/simulavrxx/m4/AX_AVR_ENVIRON.m4
U greg/simulavrxx/m4/README
U greg/simulavrxx/m4/ac_pkg_swig.m4
U greg/simulavrxx/m4/ac_python_devel.m4
U greg/simulavrxx/m4/avr_local.m4
U greg/simulavrxx/m4/avr_python.m4
U greg/simulavrxx/m4/avr_swig.m4
U greg/simulavrxx/m4/avr_tcl.m4
U greg/simulavrxx/m4/enable-tcl.m4
U greg/simulavrxx/m4/swig_enable_cxx.m4
U greg/simulavrxx/m4/swig_multi_module_support.m4
U greg/simulavrxx/m4/swig_python.m4
cvs checkout: Updating greg/simulavrxx/regress
U greg/simulavrxx/regress/.cvsignore
U greg/simulavrxx/regress/Makefile.am
U greg/simulavrxx/regress/README
U greg/simulavrxx/regress/regress.py.in
cvs checkout: Updating greg/simulavrxx/regress/avrtest
U greg/simulavrxx/regress/avrtest/.cvsignore
U greg/simulavrxx/regress/avrtest/Makefile.am
U greg/simulavrxx/regress/avrtest/avrtest_help.c
U greg/simulavrxx/regress/avrtest/avrtest_help.h
U greg/simulavrxx/regress/avrtest/test_abort.c
U greg/simulavrxx/regress/avrtest/test_exit.c
U greg/simulavrxx/regress/avrtest/test_maxruntime.c
cvs checkout: Updating greg/simulavrxx/regress/modules
U greg/simulavrxx/regress/modules/.cvsignore
U greg/simulavrxx/regress/modules/Makefile.am
U greg/simulavrxx/regress/modules/avr_target.py
U greg/simulavrxx/regress/modules/base_test.py
U greg/simulavrxx/regress/modules/gdb_rsp.py
U greg/simulavrxx/regress/modules/registers.py
cvs checkout: Updating greg/simulavrxx/regress/test_opcodes
U greg/simulavrxx/regress/test_opcodes/.cvsignore
U greg/simulavrxx/regress/test_opcodes/Makefile.am
U greg/simulavrxx/regress/test_opcodes/TODO
U greg/simulavrxx/regress/test_opcodes/test_ADC.py
U greg/simulavrxx/regress/test_opcodes/test_ADD.py
U greg/simulavrxx/regress/test_opcodes/test_ADIW.py
U greg/simulavrxx/regress/test_opcodes/test_AND.py
U greg/simulavrxx/regress/test_opcodes/test_ANDI.py
U greg/simulavrxx/regress/test_opcodes/test_ASR.py
U greg/simulavrxx/regress/test_opcodes/test_BCLR.py
U greg/simulavrxx/regress/test_opcodes/test_BLD.py
U greg/simulavrxx/regress/test_opcodes/test_BRBC.py
U greg/simulavrxx/regress/test_opcodes/test_BRBS.py
U greg/simulavrxx/regress/test_opcodes/test_BSET.py
U greg/simulavrxx/regress/test_opcodes/test_BST.py
U greg/simulavrxx/regress/test_opcodes/test_CALL.py
U greg/simulavrxx/regress/test_opcodes/test_COM.py
U greg/simulavrxx/regress/test_opcodes/test_CP.py
U greg/simulavrxx/regress/test_opcodes/test_CPC.py
U greg/simulavrxx/regress/test_opcodes/test_CPI.py
U greg/simulavrxx/regress/test_opcodes/test_CPSE.py
U greg/simulavrxx/regress/test_opcodes/test_DEC.py
U greg/simulavrxx/regress/test_opcodes/test_EOR.py
U greg/simulavrxx/regress/test_opcodes/test_ICALL.py
U greg/simulavrxx/regress/test_opcodes/test_IJMP.py
U greg/simulavrxx/regress/test_opcodes/test_INC.py
U greg/simulavrxx/regress/test_opcodes/test_JMP.py
U greg/simulavrxx/regress/test_opcodes/test_LDD_Y.py
U greg/simulavrxx/regress/test_opcodes/test_LDD_Z.py
U greg/simulavrxx/regress/test_opcodes/test_LDI.py
U greg/simulavrxx/regress/test_opcodes/test_LDS.py
U greg/simulavrxx/regress/test_opcodes/test_LD_X.py
U greg/simulavrxx/regress/test_opcodes/test_LD_X_decr.py
U greg/simulavrxx/regress/test_opcodes/test_LD_X_incr.py
U greg/simulavrxx/regress/test_opcodes/test_LD_Y_decr.py
U greg/simulavrxx/regress/test_opcodes/test_LD_Y_incr.py
U greg/simulavrxx/regress/test_opcodes/test_LD_Z_decr.py
U greg/simulavrxx/regress/test_opcodes/test_LD_Z_incr.py
U greg/simulavrxx/regress/test_opcodes/test_LPM.py
U greg/simulavrxx/regress/test_opcodes/test_LPM_Z.py
U greg/simulavrxx/regress/test_opcodes/test_LPM_Z_incr.py
U greg/simulavrxx/regress/test_opcodes/test_LSR.py
U greg/simulavrxx/regress/test_opcodes/test_MOV.py
U greg/simulavrxx/regress/test_opcodes/test_MOVW.py
U greg/simulavrxx/regress/test_opcodes/test_MUL.py
U greg/simulavrxx/regress/test_opcodes/test_MULS.py
U greg/simulavrxx/regress/test_opcodes/test_MULSU.py
U greg/simulavrxx/regress/test_opcodes/test_NEG.py
U greg/simulavrxx/regress/test_opcodes/test_NOP.py
U greg/simulavrxx/regress/test_opcodes/test_OR.py
U greg/simulavrxx/regress/test_opcodes/test_ORI.py
U greg/simulavrxx/regress/test_opcodes/test_POP.py
U greg/simulavrxx/regress/test_opcodes/test_PUSH.py
U greg/simulavrxx/regress/test_opcodes/test_RCALL.py
U greg/simulavrxx/regress/test_opcodes/test_RET.py
U greg/simulavrxx/regress/test_opcodes/test_RETI.py
U greg/simulavrxx/regress/test_opcodes/test_RJMP.py
U greg/simulavrxx/regress/test_opcodes/test_ROR.py
U greg/simulavrxx/regress/test_opcodes/test_SBC.py
U greg/simulavrxx/regress/test_opcodes/test_SBCI.py
U greg/simulavrxx/regress/test_opcodes/test_SBIW.py
U greg/simulavrxx/regress/test_opcodes/test_SBRC.py
U greg/simulavrxx/regress/test_opcodes/test_SBRS.py
U greg/simulavrxx/regress/test_opcodes/test_STD_Y.py
U greg/simulavrxx/regress/test_opcodes/test_STD_Z.py
U greg/simulavrxx/regress/test_opcodes/test_STS.py
U greg/simulavrxx/regress/test_opcodes/test_ST_X.py
U greg/simulavrxx/regress/test_opcodes/test_ST_X_decr.py
U greg/simulavrxx/regress/test_opcodes/test_ST_X_incr.py
U greg/simulavrxx/regress/test_opcodes/test_ST_Y_decr.py
U greg/simulavrxx/regress/test_opcodes/test_ST_Y_incr.py
U greg/simulavrxx/regress/test_opcodes/test_ST_Z_decr.py
U greg/simulavrxx/regress/test_opcodes/test_ST_Z_incr.py
U greg/simulavrxx/regress/test_opcodes/test_SUB.py
U greg/simulavrxx/regress/test_opcodes/test_SUBI.py
U greg/simulavrxx/regress/test_opcodes/test_SWAP.py
cvs checkout: Updating greg/simulavrxx/src
U greg/simulavrxx/src/.cvsignore
U greg/simulavrxx/src/Makefile.am
U greg/simulavrxx/src/adcpin.cpp
U greg/simulavrxx/src/adcpin.h
U greg/simulavrxx/src/application.cpp
U greg/simulavrxx/src/application.h
U greg/simulavrxx/src/at4433.cpp
U greg/simulavrxx/src/at4433.h
U greg/simulavrxx/src/at8515.cpp
U greg/simulavrxx/src/at8515.h
U greg/simulavrxx/src/atmega128.cpp
U greg/simulavrxx/src/atmega128.h
U greg/simulavrxx/src/atmega168.h
U greg/simulavrxx/src/atmega48.cpp
U greg/simulavrxx/src/atmega48.h
U greg/simulavrxx/src/atmega668base.cpp
U greg/simulavrxx/src/atmega668base.h
U greg/simulavrxx/src/atmega88.h
U greg/simulavrxx/src/avrdevice.cpp
U greg/simulavrxx/src/avrdevice.h
U greg/simulavrxx/src/avrdevice_impl.h
U greg/simulavrxx/src/avrerror.cpp
U greg/simulavrxx/src/avrerror.h
U greg/simulavrxx/src/avrfactory.cpp
U greg/simulavrxx/src/avrfactory.h
U greg/simulavrxx/src/avrmalloc.cpp
U greg/simulavrxx/src/avrmalloc.h
U greg/simulavrxx/src/breakpoint.h
U greg/simulavrxx/src/config.h.in
U greg/simulavrxx/src/config_deprecated.h
U greg/simulavrxx/src/decoder.cpp
U greg/simulavrxx/src/decoder.h
U greg/simulavrxx/src/decoder_trace.cpp
U greg/simulavrxx/src/externaltype.h
U greg/simulavrxx/src/flash.cpp
U greg/simulavrxx/src/flash.h
U greg/simulavrxx/src/funktor.h
U greg/simulavrxx/src/gdb.h
U greg/simulavrxx/src/gdbserver.cpp
U greg/simulavrxx/src/global.h
U greg/simulavrxx/src/hardware.cpp
U greg/simulavrxx/src/hardware.h
U greg/simulavrxx/src/helper.cpp
U greg/simulavrxx/src/helper.h
U greg/simulavrxx/src/hwacomp.cpp
U greg/simulavrxx/src/hwacomp.h
U greg/simulavrxx/src/hwad.cpp
U greg/simulavrxx/src/hwad.h
U greg/simulavrxx/src/hweeprom.cpp
U greg/simulavrxx/src/hweeprom.h
U greg/simulavrxx/src/hwextirq.cpp
U greg/simulavrxx/src/hwextirq.h
U greg/simulavrxx/src/hwmega48extirq.cpp
U greg/simulavrxx/src/hwmega48extirq.h
U greg/simulavrxx/src/hwmegaextirq.cpp
U greg/simulavrxx/src/hwmegaextirq.h
U greg/simulavrxx/src/hwmegatimer.cpp
U greg/simulavrxx/src/hwmegatimer.h
U greg/simulavrxx/src/hwmegatimer0123irq.cpp
U greg/simulavrxx/src/hwmegatimer0123irq.h
U greg/simulavrxx/src/hwmegax8timer.cpp
U greg/simulavrxx/src/hwmegax8timer.h
U greg/simulavrxx/src/hwmegax8timerirq.cpp
U greg/simulavrxx/src/hwmegax8timerirq.h
U greg/simulavrxx/src/hwpinchange.cpp
U greg/simulavrxx/src/hwpinchange.h
U greg/simulavrxx/src/hwport.cpp
U greg/simulavrxx/src/hwport.h
U greg/simulavrxx/src/hwspi.cpp
U greg/simulavrxx/src/hwspi.h
U greg/simulavrxx/src/hwsreg.cpp
U greg/simulavrxx/src/hwsreg.h
U greg/simulavrxx/src/hwstack.cpp
U greg/simulavrxx/src/hwstack.h
U greg/simulavrxx/src/hwtimer.cpp
U greg/simulavrxx/src/hwtimer.h
U greg/simulavrxx/src/hwtimer01irq.cpp
U greg/simulavrxx/src/hwtimer01irq.h
U greg/simulavrxx/src/hwuart.cpp
U greg/simulavrxx/src/hwuart.h
U greg/simulavrxx/src/hwwado.cpp
U greg/simulavrxx/src/hwwado.h
U greg/simulavrxx/src/ioregs.cpp
U greg/simulavrxx/src/ioregs.h
U greg/simulavrxx/src/irqsystem.cpp
U greg/simulavrxx/src/irqsystem.h
U greg/simulavrxx/src/kbdgentables.cpp
U greg/simulavrxx/src/keyboard.cpp
U greg/simulavrxx/src/keyboard.h
U greg/simulavrxx/src/keynumber_to_scancode.dat
U greg/simulavrxx/src/keytrans.h
U greg/simulavrxx/src/lcd.cpp
U greg/simulavrxx/src/lcd.h
U greg/simulavrxx/src/main.cpp
U greg/simulavrxx/src/memory.cpp
U greg/simulavrxx/src/memory.h
U greg/simulavrxx/src/mysocket.cpp
U greg/simulavrxx/src/mysocket.h
U greg/simulavrxx/src/net.cpp
U greg/simulavrxx/src/net.h
U greg/simulavrxx/src/pin.cpp
U greg/simulavrxx/src/pin.h
U greg/simulavrxx/src/pinatport.cpp
U greg/simulavrxx/src/pinatport.h
U greg/simulavrxx/src/pinmon.cpp
U greg/simulavrxx/src/pinmon.h
U greg/simulavrxx/src/pinnotify.h
U greg/simulavrxx/src/printable.cpp
U greg/simulavrxx/src/printable.h
U greg/simulavrxx/src/pysimulavr.i
U greg/simulavrxx/src/rwmem.cpp
U greg/simulavrxx/src/rwmem.h
U greg/simulavrxx/src/scope.cpp
U greg/simulavrxx/src/scope.h
U greg/simulavrxx/src/serialrx.cpp
U greg/simulavrxx/src/serialrx.h
U greg/simulavrxx/src/serialtx.cpp
U greg/simulavrxx/src/serialtx.h
U greg/simulavrxx/src/simulationmember.h
U greg/simulavrxx/src/simulavr.i
U greg/simulavrxx/src/spisink.cpp
U greg/simulavrxx/src/spisink.h
U greg/simulavrxx/src/spisrc.cpp
U greg/simulavrxx/src/spisrc.h
U greg/simulavrxx/src/string2.cpp
U greg/simulavrxx/src/string2.h
U greg/simulavrxx/src/string2_template.h
U greg/simulavrxx/src/systemclock.cpp
U greg/simulavrxx/src/systemclock.h
U greg/simulavrxx/src/systemclocktypes.h
U greg/simulavrxx/src/trace.cpp
U greg/simulavrxx/src/trace.h
U greg/simulavrxx/src/types.h
U greg/simulavrxx/src/ui.cpp
U greg/simulavrxx/src/ui.h
U greg/simulavrxx/src/vpi.cpp
U greg/simulavrxx/src/xcode_to_keynumber.dat
cvs checkout: Updating greg/simulavrxx/src/python
U greg/simulavrxx/src/python/Makefile.am
cvs checkout: Updating greg/simulavrxx/tests
]0;address@hidden:~/projects/avr/address@hidden sim]$ ls grep[Kg
CVS/  CVSROOT/  simulavr/  simulavrxx/
]0;address@hidden:~/projects/avr/address@hidden sim]$ ls ge[Kreg 
[K//s*[K[K[Ks*
greg/simulavr:
AUTHORS         COPYING             ProjSummary      simulavr.1.in
avr/            CVS/                python/          simulavr-disp.1.in
bootstrap*      dev/                README           simulavr.spec.in
ChangeLog       doc/                README.cygwin    src/
ChangeLog-2001  gdb-patches/        README.ext_int   test_asm/
ChangeLog-2002  INSTALL             README.gdb       test_c/
ChangeLog-2003  Makefile.am         README.mem_vdev  TODO
config/         Makefile_AVR_Rules  README.opcodes
configure.ac    misc/               regress/

greg/simulavrxx:
AUTHORS          config/       doc/       Makefile.am    README.gdb  tests/
autom4te.cache/  configure.ac  examples/  make_tarball*  regress/    TODO
bootstrap*       COPYING       INSTALL    NEWS           src/
ChangeLog        CVS/          m4/        README         SUPPORT
]0;address@hidden:~/projects/avr/address@hidden sim]$ exit
exit

Script done on Sun 10 Jan 2010 05:00:55 PM CST

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