Re: [Simulavr-devel] modification of AVR simulator for SCA

[Albrecht Frenzel]

Here is a listing of very strange debugging session on simulavr w/ 
atmega 328p:

> (gdb) load
> Loading section .text, size 0x1f2 lma 0x7e00
> Loading section .version, size 0x2 lma 0x7ffe
> Start address 0x7e00, load size 500
> Transfer rate: 244 KB/sec, 250 bytes/write.
> (gdb) i r
> ...
> r28            0xaa    170
> r29            0xaa    170
> r30            0xaa    170
> r31            0xaa    170
> SREG           0x0    0
> SP             0x0    0x0
> PC2            0x7e00    32256
> pc             0x7e00    0x7e00 <main>
> (gdb) stepi
> 0x00007e02 in main () at optiboot.c:452
>    0x00007e00 <main+0>:    1f 92    push    r1
> => 0x00007e02 <main+2>:    cd b7    in    r28, 0x3d    ; 61
>    0x00007e04 <main+4>:    de b7    in    r29, 0x3e    ; 62
> (gdb) i r
> ...
> r28            0xaa    170
> r29            0xaa    170
> r30            0xaa    170
> r31            0xaa    170
> SREG           0x0    0
> SP             0x80ffff    0x80ffff
> PC2            0x7e02    32258
> pc             0x7e02    0x7e02 <main+2>
> (gdb) 

After the load command SP is 0 - the reset bug.
The first instruction a 0x7e00 is push r1
This instruction should crash the simulator with assert(0 != 
SP_value), but it doesn't. Instead SP wraps around to 0x80ffff.

Something goes badly wrong: Sometimes the assertion is thrown, 
sometimes not.