Re: [lwip-users] Problem running lwip on cortex M7 with D cache enabled

[jochen]

Hi Noam,

thanks for the fast reply. I was hoping not to update lwip (Atmel's ASF 
still claims on lwip 1.4.1, CMSIS 4.0 and FreeRTOS 8.3...) but I'll look 
into that.

Remaining questions :
- descriptors are hard coded == placed in no cache memory ?
- what about RX/TX buffers: also placed in no cache memory or do you 
manage the cache after GMAC DMA e.g. using cache clean / invalidate ?
- what about the ethernet / gmac driver for STM32F7 ? Which driver do 
you use, did you patch the old driver as recommended here 
http://www.nuttx.org/doku.php?id=wiki:howtos:port-drivers_stm32f7 or is 
this driver already available in the STM or lwip source code package ?

Regards,
Jochen



Am 30.11.2017 12:37, schrieb Noam Weissman:

> Hi,
>
> I am working with STM32F7 with LwIP 2.02 + FreeRTOS 9
>
> D and I cache are enabled.
>
> TX/RX descriptors are hard coded inside DTCM. We have no problems for 
> now.
>
> Most of the rest of LwIP init is as it was in older projects that used 
> the STM32F4
>
> I strongly suggest upgrading to LwIP 2.02 or even 2.03
>
> BR,
> Noam.
>
> -----Original Message-----
> From: lwip-users [mailto:address@hidden 
> On Behalf Of Jochen Strohbeck
> Sent: Thursday, November 30, 2017 2:10 PM
> To: address@hidden
> Subject: [lwip-users] Problem running lwip on cortex M7 with D cache 
> enabled
>
> Hello,
>
> I'm using lwip 1.4.1 and FreeRTOS on a SAME70 custom board with success 
> if D-cache is disabled. If I enable the D-cache no more packets are 
> received. If I place the RX descriptor into a non-cacheable region I 
> get packets again but the received data is corrupt. Here is the lwip 
> output:
>
> Checksum (0xa5fd) failed, IP packet dropped.
> IP (len 96) is longer than pbuf (len 50), IP packet dropped.
>
> I understand that I have to move the receive (and send) buffers which 
> are used by the GMAC DMA to a non-cacheable region too. And here is 
> where my problem starts. In my understanding these buffers are by 
> default in an lwip memory pool. If I simply place the entire memory 
> pool to non-cacheable region the CPU hangs up. I guess this is due to 
> the D-cache requirements that the (GMAC) DMA buffer must be aligned to 
> 32bytes but I don't know how to modify the lwip code in such a way that 
> the receive buffer (pbuf->payload?) is 32byte aligned. The other (and
> better?) way would be to separate the receive buffer (or pbuf->payload) 
> from the lwip memory pool so I can place it everywhere I want but I 
> don't know how to manage this. Probably there is a better way to do so 
> in lwip ?
>
> Any help is welcome.
>
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