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[Qemu-arm] [PATCH v3 07/31] arm/translate-a64: handle_3same_64 comment f
From: |
Alex Bennée |
Subject: |
[Qemu-arm] [PATCH v3 07/31] arm/translate-a64: handle_3same_64 comment fix |
Date: |
Fri, 23 Feb 2018 15:36:12 +0000 |
We do implement all the opcodes.
Signed-off-by: Alex Bennée <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
---
target/arm/translate-a64.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index ebaf4571ac..5dd54b7ac4 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -7278,8 +7278,7 @@ static void handle_3same_64(DisasContext *s, int opcode,
bool u,
/* Handle 64x64->64 opcodes which are shared between the scalar
* and vector 3-same groups. We cover every opcode where size == 3
* is valid in either the three-reg-same (integer, not pairwise)
- * or scalar-three-reg-same groups. (Some opcodes are not yet
- * implemented.)
+ * or scalar-three-reg-same groups.
*/
TCGCond cond;
--
2.15.1
- [Qemu-arm] [PATCH v3 00/31] Add ARMv8.2 half-precision functions, Alex Bennée, 2018/02/23
- [Qemu-arm] [PATCH v3 02/31] target/arm/cpu64: introduce ARM_V8_FP16 feature bit, Alex Bennée, 2018/02/23
- [Qemu-arm] [PATCH v3 03/31] target/arm/cpu.h: update comment for half-precision values, Alex Bennée, 2018/02/23
- [Qemu-arm] [PATCH v3 01/31] include/exec/helper-head.h: support f16 in helper calls, Alex Bennée, 2018/02/23
- [Qemu-arm] [PATCH v3 04/31] target/arm/cpu.h: add additional float_status flags, Alex Bennée, 2018/02/23
- [Qemu-arm] [PATCH v3 05/31] target/arm/helper: pass explicit fpst to set_rmode, Alex Bennée, 2018/02/23
- [Qemu-arm] [PATCH v3 06/31] arm/translate-a64: implement half-precision F(MIN|MAX)(V|NMV), Alex Bennée, 2018/02/23
- [Qemu-arm] [PATCH v3 07/31] arm/translate-a64: handle_3same_64 comment fix,
Alex Bennée <=
- [Qemu-arm] [PATCH v3 08/31] arm/translate-a64: initial decode for simd_three_reg_same_fp16, Alex Bennée, 2018/02/23
- [Qemu-arm] [PATCH v3 10/31] arm/translate-a64: add FP16 F[A]C[EQ/GE/GT] to simd_three_reg_same_fp16, Alex Bennée, 2018/02/23
- [Qemu-arm] [PATCH v3 13/31] arm/translate-a64: add FP16 pairwise ops simd_three_reg_same_fp16, Alex Bennée, 2018/02/23
- [Qemu-arm] [PATCH v3 09/31] arm/translate-a64: add FP16 FADD/FABD/FSUB/FMUL/FDIV to simd_three_reg_same_fp16, Alex Bennée, 2018/02/23
- [Qemu-arm] [PATCH v3 18/31] arm/translate-a64: add FCVTxx to simd_two_reg_misc_fp16, Alex Bennée, 2018/02/23
- [Qemu-arm] [PATCH v3 30/31] arm/translate-a64: implement simd_scalar_three_reg_same_fp16, Alex Bennée, 2018/02/23
- [Qemu-arm] [PATCH v3 16/31] arm/translate-a64: initial decode for simd_two_reg_misc_fp16, Alex Bennée, 2018/02/23
- [Qemu-arm] [PATCH v3 17/31] arm/translate-a64: add FP16 FPRINTx to simd_two_reg_misc_fp16, Alex Bennée, 2018/02/23