[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH 11/17] target/arm: do S1_ptw_translate() before address space loo
From: |
remi . denis . courmont |
Subject: |
[PATCH 11/17] target/arm: do S1_ptw_translate() before address space lookup |
Date: |
Mon, 9 Nov 2020 16:10:14 +0200 |
From: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
In the secure stage 2 translation regime, the VSTCR.SW and VTCR.NSW
bits can invert the secure flag for pagetable walks. This patchset
allows S1_ptw_translate() to change the non-secure bit.
Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
---
target/arm/helper.c | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 2263715ba4..90967771b6 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -10391,7 +10391,7 @@ static bool get_level1_table_address(CPUARMState *env,
ARMMMUIdx mmu_idx,
/* Translate a S1 pagetable walk through S2 if needed. */
static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
- hwaddr addr, MemTxAttrs txattrs,
+ hwaddr addr, bool *is_secure,
ARMMMUFaultInfo *fi)
{
ARMMMUIdx s2_mmu_idx;
@@ -10403,6 +10403,9 @@ static hwaddr S1_ptw_translate(CPUARMState *env,
ARMMMUIdx mmu_idx,
int s2prot;
int ret;
ARMCacheAttrs cacheattrs = {};
+ MemTxAttrs txattrs = {};
+
+ assert(!*is_secure); /* TODO: S-EL2 */
ret = get_phys_addr_lpae(env, addr, MMU_DATA_LOAD, s2_mmu_idx, false,
&s2pa, &txattrs, &s2prot, &s2size, fi,
@@ -10441,9 +10444,9 @@ static uint32_t arm_ldl_ptw(CPUState *cs, hwaddr addr,
bool is_secure,
AddressSpace *as;
uint32_t data;
+ addr = S1_ptw_translate(env, mmu_idx, addr, &is_secure, fi);
attrs.secure = is_secure;
as = arm_addressspace(cs, attrs);
- addr = S1_ptw_translate(env, mmu_idx, addr, attrs, fi);
if (fi->s1ptw) {
return 0;
}
@@ -10470,9 +10473,9 @@ static uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr,
bool is_secure,
AddressSpace *as;
uint64_t data;
+ addr = S1_ptw_translate(env, mmu_idx, addr, &is_secure, fi);
attrs.secure = is_secure;
as = arm_addressspace(cs, attrs);
- addr = S1_ptw_translate(env, mmu_idx, addr, attrs, fi);
if (fi->s1ptw) {
return 0;
}
--
2.29.2
- [PATCHv2 00/17] ARM Secure EL2 extension, Rémi Denis-Courmont, 2020/11/09
- [PATCH 01/17] target/arm: remove redundant tests, remi . denis . courmont, 2020/11/09
- [PATCH 05/17] target/arm: factor MDCR_EL2 common handling, remi . denis . courmont, 2020/11/09
- [PATCH 02/17] target/arm: add arm_is_el2_enabled() helper, remi . denis . courmont, 2020/11/09
- [PATCH 03/17] target/arm: use arm_is_el2_enabled() where applicable, remi . denis . courmont, 2020/11/09
- [PATCH 07/17] target/arm: add 64-bit S-EL2 to EL exception table, remi . denis . courmont, 2020/11/09
- [PATCH 04/17] target/arm: use arm_hcr_el2_eff() where applicable, remi . denis . courmont, 2020/11/09
- [PATCH 06/17] target/arm: declare new AA64PFR0 bit-fields, remi . denis . courmont, 2020/11/09
- [PATCH 11/17] target/arm: do S1_ptw_translate() before address space lookup,
remi . denis . courmont <=
- [PATCH 08/17] target/arm: return the stage 2 index for stage 1, remi . denis . courmont, 2020/11/09
- [PATCH 09/17] target/arm: add MMU stage 1 for Secure EL2, remi . denis . courmont, 2020/11/09
- [PATCH 14/17] target/arm: set HPFAR_EL2.NS on secure stage 2 faults, remi . denis . courmont, 2020/11/09
- [PATCH 15/17] target/arm: add ARMv8.4-SEL2 extension, remi . denis . courmont, 2020/11/09
- [PATCH 17/17] target/arm: refactor vae1_tlbmask(), remi . denis . courmont, 2020/11/09
- [PATCH 10/17] target/arm: add ARMv8.4-SEL2 system registers, remi . denis . courmont, 2020/11/09