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Re: [PATCH 28/71] target/arm: Add PSTATE.{SM,ZA} to TB flags
From: |
Peter Maydell |
Subject: |
Re: [PATCH 28/71] target/arm: Add PSTATE.{SM,ZA} to TB flags |
Date: |
Mon, 6 Jun 2022 16:58:16 +0100 |
On Thu, 2 Jun 2022 at 23:22, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> These are required to determine if various insns
> are allowed to issue.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/arm/cpu.h | 2 ++
> target/arm/translate.h | 4 ++++
> target/arm/helper.c | 4 ++++
> target/arm/translate-a64.c | 2 ++
> 4 files changed, 12 insertions(+)
>
> diff --git a/target/arm/cpu.h b/target/arm/cpu.h
> index 1ae1b7122b..9bd8058afe 100644
> --- a/target/arm/cpu.h
> +++ b/target/arm/cpu.h
> @@ -3284,6 +3284,8 @@ FIELD(TBFLAG_A64, TCMA, 16, 2)
> FIELD(TBFLAG_A64, MTE_ACTIVE, 18, 1)
> FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1)
> FIELD(TBFLAG_A64, SMEEXC_EL, 20, 2)
> +FIELD(TBFLAG_A64, PSTATE_SM, 22, 1)
> +FIELD(TBFLAG_A64, PSTATE_ZA, 23, 1)
>
> /*
> * Helpers for using the above.
> diff --git a/target/arm/translate.h b/target/arm/translate.h
> index a492e4217b..fbd6713572 100644
> --- a/target/arm/translate.h
> +++ b/target/arm/translate.h
> @@ -101,6 +101,10 @@ typedef struct DisasContext {
> bool align_mem;
> /* True if PSTATE.IL is set */
> bool pstate_il;
> + /* True if PSTATE.SM is set. */
> + bool pstate_sm;
> + /* True if PSTATE.ZA is set. */
> + bool pstate_za;
> /* True if MVE insns are definitely not predicated by VPR or LTPSIZE */
> bool mve_no_pred;
> /*
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index f852fd7644..3edecb56b6 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -13857,6 +13857,10 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState
> *env, int el, int fp_el,
> }
> if (cpu_isar_feature(aa64_sme, env_archcpu(env))) {
> DP_TBFLAG_A64(flags, SMEEXC_EL, sme_exception_el(env, el));
> + if (FIELD_EX64(env->svcr, SVCR, SM)) {
> + DP_TBFLAG_A64(flags, PSTATE_SM, 1);
> + }
> + DP_TBFLAG_A64(flags, PSTATE_ZA, FIELD_EX64(env->svcr, SVCR, ZA));
Why did you write these two differently? Don't they do the same
thing (set the tb flag to the value of the bit in env->svcr) ?
Otherwise
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
- [PATCH 13/71] target/arm: Split out load/store primitives to sve_ldst_internal.h, (continued)
- [PATCH 13/71] target/arm: Split out load/store primitives to sve_ldst_internal.h, Richard Henderson, 2022/06/02
- [PATCH 15/71] target/arm: Move expand_pred_b to vec_internal.h, Richard Henderson, 2022/06/02
- [PATCH 16/71] target/arm: Use expand_pred_b in mve_helper.c, Richard Henderson, 2022/06/02
- [PATCH 17/71] target/arm: Move expand_pred_h to vec_internal.h, Richard Henderson, 2022/06/02
- [PATCH 20/71] target/arm: Add ID_AA64SMFR0_EL1, Richard Henderson, 2022/06/02
- [PATCH 22/71] target/arm: Add SMEEXC_EL to TB flags, Richard Henderson, 2022/06/02
- [PATCH 28/71] target/arm: Add PSTATE.{SM,ZA} to TB flags, Richard Henderson, 2022/06/02
- Re: [PATCH 28/71] target/arm: Add PSTATE.{SM,ZA} to TB flags,
Peter Maydell <=
- [PATCH 18/71] target/arm: Export bfdotadd from vec_helper.c, Richard Henderson, 2022/06/02
- [PATCH 19/71] target/arm: Add isar_feature_aa64_sme, Richard Henderson, 2022/06/02
- [PATCH 14/71] target/arm: Export sve contiguous ldst support functions, Richard Henderson, 2022/06/02
- [PATCH 21/71] target/arm: Implement TPIDR2_EL0, Richard Henderson, 2022/06/02
- [PATCH 23/71] target/arm: Add syn_smetrap, Richard Henderson, 2022/06/02