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[Qemu-devel] [PATCH 0/5] tricore: adding new instructions and fixing iss


From: David Brenken
Subject: [Qemu-devel] [PATCH 0/5] tricore: adding new instructions and fixing issues
Date: Wed, 5 Jun 2019 08:11:21 +0200

From: David Brenken <address@hidden>

Hello everyone,

in the scope of this patchset we added implementations for the following 
instructions for the target TriCore:

QSEED, FTOIZ, UTOF

For the implementation of the QSEED instruction we wrote a test application to 
record the QSEED results on the actual target. We recognized that the results
of the instruction can be clustered in blocks and do not use all available 
mantissa bits.
After investigating on how to calculate the square root on floats, which can 
easily
be done using shift and add, we implemented it using a 128 entry LUT and 
finetuned
the values to exactly match the hardware results.

Furthermore we added a fix for the RRPW_INSERT instruction.

Internally we are now using QEMU head and encountered strange issues during 
execution. Sometimes the PC of the target was set to address 0x0 which was 
wrong 
behaviour. A detailed analysis (using valgrind and git bisect) resulted in the 
fix 
to reset the ctx variable before generating intermediate code.

Best regards

David Brenken


Andreas Konopik (1):
  tricore: add QSEED instruction

David Brenken (3):
  tricore: add FTOIZ instruction
  tricore: add UTOF instruction
  tricore: fix RRPW_INSERT instruction

Georg Hofstetter (1):
  tricore: reset DisasContext before generating code

 target/tricore/fpu_helper.c | 129 ++++++++++++++++++++++++++++++++++++
 target/tricore/helper.h     |   3 +
 target/tricore/translate.c  |  21 +++++-
 3 files changed, 150 insertions(+), 3 deletions(-)

-- 
2.17.1




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