Re: [Qemu-devel] [PATCH v4 0/7] tcg/ppc: Add vector opcodes

[Richard Henderson]

On 6/26/19 7:00 PM, Mark Cave-Ayland wrote:
> Interestingly if I set a trap and then switch the opcode to "lis r4,0" 
> (0x3c800000)
> then we carry on as normal until the next "lis r2,0" instruction. Looking 
> through the
> whole output of -d out_asm this is the first mention of r2 which makes me 
> wonder if
> it is special somehow? At least a quick search indicates that for 32-bit PPC 
> r2 is
> supposed to be dedicated as a TOC pointer.
> 
> Is there a quick way to disable r2 from the list of available registers to 
> see if
> that gets things going?

Interesting.  I'm not sure why that's happening.

As a quick hack,


  /* For some memory operations, we need a scratch that isn't R0.  For the AIX
     calling convention, we can re-use the TOC register since we'll be reloading
     it at every call.  Otherwise R12 will do nicely as neither a call-saved
     register nor a parameter register.  */
- #ifdef _CALL_AIX
+ #if 0
  # define TCG_REG_TMP1   TCG_REG_R2
  #else
  # define TCG_REG_TMP1   TCG_REG_R12
  #endif


But I thought that _CALL_AIX was only defined for ppc64 elf version 1.  I
thought that ppc32 used _CALL_SYSV instead.  Certainly that's what is used
elsewhere...


r~