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[PULL 37/48] target/arm: Update arm_cpu_do_interrupt_aarch64 for VHE
From: |
Peter Maydell |
Subject: |
[PULL 37/48] target/arm: Update arm_cpu_do_interrupt_aarch64 for VHE |
Date: |
Fri, 7 Feb 2020 14:33:32 +0000 |
From: Richard Henderson <address@hidden>
When VHE is enabled, the exception level below EL2 is not EL1,
but EL0, and so to identify the entry vector offset for exceptions
targeting EL2 we need to look at the width of EL0, not of EL1.
Tested-by: Alex Bennée <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/helper.c | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index ff2d957b7c6..7d15d5c933c 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -9017,14 +9017,19 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
* immediately lower than the target level is using AArch32 or AArch64
*/
bool is_aa64;
+ uint64_t hcr;
switch (new_el) {
case 3:
is_aa64 = (env->cp15.scr_el3 & SCR_RW) != 0;
break;
case 2:
- is_aa64 = (env->cp15.hcr_el2 & HCR_RW) != 0;
- break;
+ hcr = arm_hcr_el2_eff(env);
+ if ((hcr & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) {
+ is_aa64 = (hcr & HCR_RW) != 0;
+ break;
+ }
+ /* fall through */
case 1:
is_aa64 = is_a64(env);
break;
--
2.20.1
- [PULL 28/48] target/arm: Update define_one_arm_cp_reg_with_opaque for VHE, (continued)
- [PULL 28/48] target/arm: Update define_one_arm_cp_reg_with_opaque for VHE, Peter Maydell, 2020/02/07
- [PULL 31/48] target/arm: Flush tlb for ASID changes in EL2&0 translation regime, Peter Maydell, 2020/02/07
- [PULL 29/48] target/arm: Add VHE system register redirection and aliasing, Peter Maydell, 2020/02/07
- [PULL 30/48] target/arm: Add VHE timer register redirection and aliasing, Peter Maydell, 2020/02/07
- [PULL 32/48] target/arm: Flush tlbs for E2&0 translation regime, Peter Maydell, 2020/02/07
- [PULL 33/48] target/arm: Update arm_phys_excp_target_el for TGE, Peter Maydell, 2020/02/07
- [PULL 34/48] target/arm: Update {fp,sve}_exception_el for VHE, Peter Maydell, 2020/02/07
- [PULL 35/48] target/arm: check TGE and E2H flags for EL0 pauth traps, Peter Maydell, 2020/02/07
- [PULL 36/48] target/arm: Update get_a64_user_mem_index for VHE, Peter Maydell, 2020/02/07
- [PULL 38/48] target/arm: Enable ARMv8.1-VHE in -cpu max, Peter Maydell, 2020/02/07
- [PULL 37/48] target/arm: Update arm_cpu_do_interrupt_aarch64 for VHE,
Peter Maydell <=
- [PULL 40/48] target/arm: Pass more cpu state to arm_excp_unmasked, Peter Maydell, 2020/02/07
- [PULL 41/48] target/arm: Use bool for unmasked in arm_excp_unmasked, Peter Maydell, 2020/02/07
- [PULL 43/48] bcm2835_dma: Fix the ylen loop in TD mode, Peter Maydell, 2020/02/07
- [PULL 39/48] target/arm: Move arm_excp_unmasked to cpu.c, Peter Maydell, 2020/02/07
- [PULL 42/48] target/arm: Raise only one interrupt in arm_cpu_exec_interrupt, Peter Maydell, 2020/02/07
- [PULL 44/48] bcm2835_dma: Re-initialize xlen in TD mode, Peter Maydell, 2020/02/07
- [PULL 45/48] docs/arm-cpu-features: Make kvm-no-adjvtime comment clearer, Peter Maydell, 2020/02/07
- [PULL 46/48] armv7m_systick: delay timer_new to avoid memleaks, Peter Maydell, 2020/02/07
- [PULL 47/48] stm32f2xx_timer: delay timer_new to avoid memleaks, Peter Maydell, 2020/02/07
- [PULL 48/48] stellaris: delay timer_new to avoid memleaks, Peter Maydell, 2020/02/07