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[PULL 15/46] target/arm: Mask CPSR_J when Jazelle is not enabled
From: |
Peter Maydell |
Subject: |
[PULL 15/46] target/arm: Mask CPSR_J when Jazelle is not enabled |
Date: |
Thu, 13 Feb 2020 14:41:14 +0000 |
From: Richard Henderson <address@hidden>
The J bit signals Jazelle mode, and so of course is RES0
when the feature is not enabled.
Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/internals.h | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/target/arm/internals.h b/target/arm/internals.h
index 4d4896fcdcf..0569c96fd94 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -1064,7 +1064,7 @@ static inline bool arm_mmu_idx_is_stage1_of_2(ARMMMUIdx
mmu_idx)
static inline uint32_t aarch32_cpsr_valid_mask(uint64_t features,
const ARMISARegisters *id)
{
- uint32_t valid = CPSR_M | CPSR_AIF | CPSR_IL | CPSR_NZCV | CPSR_J;
+ uint32_t valid = CPSR_M | CPSR_AIF | CPSR_IL | CPSR_NZCV;
if ((features >> ARM_FEATURE_V4T) & 1) {
valid |= CPSR_T;
@@ -1078,6 +1078,9 @@ static inline uint32_t aarch32_cpsr_valid_mask(uint64_t
features,
if ((features >> ARM_FEATURE_THUMB2) & 1) {
valid |= CPSR_IT;
}
+ if (isar_feature_jazelle(id)) {
+ valid |= CPSR_J;
+ }
return valid;
}
--
2.20.1
- [PULL 03/46] bios-tables-test: prepare to change ARM virt ACPI DSDT, (continued)
- [PULL 03/46] bios-tables-test: prepare to change ARM virt ACPI DSDT, Peter Maydell, 2020/02/13
- [PULL 02/46] i.MX: Add support for WDT on i.MX6, Peter Maydell, 2020/02/13
- [PULL 06/46] arm/acpi: fix PCI _PRT definition, Peter Maydell, 2020/02/13
- [PULL 05/46] arm/virt/acpi: remove _ADR from devices identified by _HID, Peter Maydell, 2020/02/13
- [PULL 07/46] arm/acpi: fix duplicated _UID of PCI interrupt link devices, Peter Maydell, 2020/02/13
- [PULL 08/46] arm/acpi: simplify the description of PCI _CRS, Peter Maydell, 2020/02/13
- [PULL 09/46] virt/acpi: update golden masters for DSDT update, Peter Maydell, 2020/02/13
- [PULL 12/46] target/arm: Add isar_feature tests for PAN + ATS1E1, Peter Maydell, 2020/02/13
- [PULL 10/46] target/arm: Add arm_mmu_idx_is_stage1_of_2, Peter Maydell, 2020/02/13
- [PULL 14/46] target/arm: Split out aarch32_cpsr_valid_mask, Peter Maydell, 2020/02/13
- [PULL 15/46] target/arm: Mask CPSR_J when Jazelle is not enabled,
Peter Maydell <=
- [PULL 11/46] target/arm: Add mmu_idx for EL1 and EL2 w/ PAN enabled, Peter Maydell, 2020/02/13
- [PULL 19/46] target/arm: Introduce aarch64_pstate_valid_mask, Peter Maydell, 2020/02/13
- [PULL 16/46] target/arm: Replace CPSR_ERET_MASK with aarch32_cpsr_valid_mask, Peter Maydell, 2020/02/13
- [PULL 22/46] target/arm: Enforce PAN semantics in get_S1prot, Peter Maydell, 2020/02/13
- [PULL 17/46] target/arm: Use aarch32_cpsr_valid_mask in helper_exception_return, Peter Maydell, 2020/02/13
- [PULL 18/46] target/arm: Remove CPSR_RESERVED, Peter Maydell, 2020/02/13
- [PULL 21/46] target/arm: Update arm_mmu_idx_el for PAN, Peter Maydell, 2020/02/13
- [PULL 20/46] target/arm: Update MSR access for PAN, Peter Maydell, 2020/02/13
- [PULL 13/46] target/arm: Move LOR regdefs to file scope, Peter Maydell, 2020/02/13
- [PULL 23/46] target/arm: Set PAN bit as required on exception entry, Peter Maydell, 2020/02/13