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[PULL 13/46] target/arm: Move LOR regdefs to file scope
From: |
Peter Maydell |
Subject: |
[PULL 13/46] target/arm: Move LOR regdefs to file scope |
Date: |
Thu, 13 Feb 2020 14:41:12 +0000 |
From: Richard Henderson <address@hidden>
For static const regdefs, file scope is preferred.
Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/helper.c | 57 +++++++++++++++++++++++----------------------
1 file changed, 29 insertions(+), 28 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index bfd6c0d04bd..e4f17c7e839 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -6334,6 +6334,35 @@ static CPAccessResult access_lor_other(CPUARMState *env,
return access_lor_ns(env);
}
+/*
+ * A trivial implementation of ARMv8.1-LOR leaves all of these
+ * registers fixed at 0, which indicates that there are zero
+ * supported Limited Ordering regions.
+ */
+static const ARMCPRegInfo lor_reginfo[] = {
+ { .name = "LORSA_EL1", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 0,
+ .access = PL1_RW, .accessfn = access_lor_other,
+ .type = ARM_CP_CONST, .resetvalue = 0 },
+ { .name = "LOREA_EL1", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 1,
+ .access = PL1_RW, .accessfn = access_lor_other,
+ .type = ARM_CP_CONST, .resetvalue = 0 },
+ { .name = "LORN_EL1", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 2,
+ .access = PL1_RW, .accessfn = access_lor_other,
+ .type = ARM_CP_CONST, .resetvalue = 0 },
+ { .name = "LORC_EL1", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 3,
+ .access = PL1_RW, .accessfn = access_lor_other,
+ .type = ARM_CP_CONST, .resetvalue = 0 },
+ { .name = "LORID_EL1", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 7,
+ .access = PL1_R, .accessfn = access_lorid,
+ .type = ARM_CP_CONST, .resetvalue = 0 },
+ REGINFO_SENTINEL
+};
+
#ifdef TARGET_AARCH64
static CPAccessResult access_pauth(CPUARMState *env, const ARMCPRegInfo *ri,
bool isread)
@@ -7568,34 +7597,6 @@ void register_cp_regs_for_features(ARMCPU *cpu)
}
if (cpu_isar_feature(aa64_lor, cpu)) {
- /*
- * A trivial implementation of ARMv8.1-LOR leaves all of these
- * registers fixed at 0, which indicates that there are zero
- * supported Limited Ordering regions.
- */
- static const ARMCPRegInfo lor_reginfo[] = {
- { .name = "LORSA_EL1", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 0,
- .access = PL1_RW, .accessfn = access_lor_other,
- .type = ARM_CP_CONST, .resetvalue = 0 },
- { .name = "LOREA_EL1", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 1,
- .access = PL1_RW, .accessfn = access_lor_other,
- .type = ARM_CP_CONST, .resetvalue = 0 },
- { .name = "LORN_EL1", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 2,
- .access = PL1_RW, .accessfn = access_lor_other,
- .type = ARM_CP_CONST, .resetvalue = 0 },
- { .name = "LORC_EL1", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 3,
- .access = PL1_RW, .accessfn = access_lor_other,
- .type = ARM_CP_CONST, .resetvalue = 0 },
- { .name = "LORID_EL1", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 7,
- .access = PL1_R, .accessfn = access_lorid,
- .type = ARM_CP_CONST, .resetvalue = 0 },
- REGINFO_SENTINEL
- };
define_arm_cp_regs(cpu, lor_reginfo);
}
--
2.20.1
- [PULL 14/46] target/arm: Split out aarch32_cpsr_valid_mask, (continued)
- [PULL 14/46] target/arm: Split out aarch32_cpsr_valid_mask, Peter Maydell, 2020/02/13
- [PULL 15/46] target/arm: Mask CPSR_J when Jazelle is not enabled, Peter Maydell, 2020/02/13
- [PULL 11/46] target/arm: Add mmu_idx for EL1 and EL2 w/ PAN enabled, Peter Maydell, 2020/02/13
- [PULL 19/46] target/arm: Introduce aarch64_pstate_valid_mask, Peter Maydell, 2020/02/13
- [PULL 16/46] target/arm: Replace CPSR_ERET_MASK with aarch32_cpsr_valid_mask, Peter Maydell, 2020/02/13
- [PULL 22/46] target/arm: Enforce PAN semantics in get_S1prot, Peter Maydell, 2020/02/13
- [PULL 17/46] target/arm: Use aarch32_cpsr_valid_mask in helper_exception_return, Peter Maydell, 2020/02/13
- [PULL 18/46] target/arm: Remove CPSR_RESERVED, Peter Maydell, 2020/02/13
- [PULL 21/46] target/arm: Update arm_mmu_idx_el for PAN, Peter Maydell, 2020/02/13
- [PULL 20/46] target/arm: Update MSR access for PAN, Peter Maydell, 2020/02/13
- [PULL 13/46] target/arm: Move LOR regdefs to file scope,
Peter Maydell <=
- [PULL 23/46] target/arm: Set PAN bit as required on exception entry, Peter Maydell, 2020/02/13
- [PULL 27/46] target/arm: Update MSR access to UAO, Peter Maydell, 2020/02/13
- [PULL 26/46] target/arm: Add ID_AA64MMFR2_EL1, Peter Maydell, 2020/02/13
- [PULL 24/46] target/arm: Implement ATS1E1 system registers, Peter Maydell, 2020/02/13
- [PULL 25/46] target/arm: Enable ARMv8.2-ATS1E1 in -cpu max, Peter Maydell, 2020/02/13
- [PULL 30/46] hw/arm: ast2400/ast2500: Wire up EHCI controllers, Peter Maydell, 2020/02/13
- [PULL 28/46] target/arm: Implement UAO semantics, Peter Maydell, 2020/02/13
- [PULL 29/46] target/arm: Enable ARMv8.2-UAO in -cpu max, Peter Maydell, 2020/02/13
- [PULL 31/46] hw/arm: ast2600: Wire up EHCI controllers, Peter Maydell, 2020/02/13
- [PULL 32/46] hw/char/exynos4210_uart: Fix memleaks in exynos4210_uart_init, Peter Maydell, 2020/02/13