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[PATCH v2 06/17] target/arm: Perform fpdp_v2 check first
From: |
Richard Henderson |
Subject: |
[PATCH v2 06/17] target/arm: Perform fpdp_v2 check first |
Date: |
Mon, 24 Feb 2020 14:22:21 -0800 |
Shuffle the order of the checks so that we test the ISA
before we test anything else, such as the register arguments.
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/translate-vfp.inc.c | 140 +++++++++++++++++----------------
1 file changed, 71 insertions(+), 69 deletions(-)
diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c
index e94876c30c..ff30165045 100644
--- a/target/arm/translate-vfp.inc.c
+++ b/target/arm/translate-vfp.inc.c
@@ -200,13 +200,13 @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a)
return false;
}
- /* UNDEF accesses to D16-D31 if they don't exist */
- if (dp && !dc_isar_feature(aa32_simd_r32, s) &&
- ((a->vm | a->vn | a->vd) & 0x10)) {
+ if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
- if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
+ /* UNDEF accesses to D16-D31 if they don't exist */
+ if (dp && !dc_isar_feature(aa32_simd_r32, s) &&
+ ((a->vm | a->vn | a->vd) & 0x10)) {
return false;
}
@@ -333,13 +333,13 @@ static bool trans_VMINMAXNM(DisasContext *s,
arg_VMINMAXNM *a)
return false;
}
- /* UNDEF accesses to D16-D31 if they don't exist */
- if (dp && !dc_isar_feature(aa32_simd_r32, s) &&
- ((a->vm | a->vn | a->vd) & 0x10)) {
+ if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
- if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
+ /* UNDEF accesses to D16-D31 if they don't exist */
+ if (dp && !dc_isar_feature(aa32_simd_r32, s) &&
+ ((a->vm | a->vn | a->vd) & 0x10)) {
return false;
}
@@ -419,13 +419,13 @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a)
return false;
}
- /* UNDEF accesses to D16-D31 if they don't exist */
- if (dp && !dc_isar_feature(aa32_simd_r32, s) &&
- ((a->vm | a->vd) & 0x10)) {
+ if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
- if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
+ /* UNDEF accesses to D16-D31 if they don't exist */
+ if (dp && !dc_isar_feature(aa32_simd_r32, s) &&
+ ((a->vm | a->vd) & 0x10)) {
return false;
}
@@ -483,12 +483,12 @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a)
return false;
}
- /* UNDEF accesses to D16-D31 if they don't exist */
- if (dp && !dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) {
+ if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
- if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
+ /* UNDEF accesses to D16-D31 if they don't exist */
+ if (dp && !dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) {
return false;
}
@@ -1308,12 +1308,12 @@ static bool do_vfp_3op_dp(DisasContext *s,
VFPGen3OpDPFn *fn,
TCGv_i64 f0, f1, fd;
TCGv_ptr fpst;
- /* UNDEF accesses to D16-D31 if they don't exist */
- if (!dc_isar_feature(aa32_simd_r32, s) && ((vd | vn | vm) & 0x10)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
+ /* UNDEF accesses to D16-D31 if they don't exist */
+ if (!dc_isar_feature(aa32_simd_r32, s) && ((vd | vn | vm) & 0x10)) {
return false;
}
@@ -1457,12 +1457,12 @@ static bool do_vfp_2op_dp(DisasContext *s,
VFPGen2OpDPFn *fn, int vd, int vm)
int veclen = s->vec_len;
TCGv_i64 f0, fd;
- /* UNDEF accesses to D16-D31 if they don't exist */
- if (!dc_isar_feature(aa32_simd_r32, s) && ((vd | vm) & 0x10)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
+ /* UNDEF accesses to D16-D31 if they don't exist */
+ if (!dc_isar_feature(aa32_simd_r32, s) && ((vd | vm) & 0x10)) {
return false;
}
@@ -1827,7 +1827,9 @@ static bool trans_VFM_dp(DisasContext *s, arg_VFM_dp *a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
+ /* UNDEF accesses to D16-D31 if they don't exist. */
+ if (!dc_isar_feature(aa32_simd_r32, s) &&
+ ((a->vd | a->vn | a->vm) & 0x10)) {
return false;
}
@@ -1921,12 +1923,12 @@ static bool trans_VMOV_imm_dp(DisasContext *s,
arg_VMOV_imm_dp *a)
vd = a->vd;
- /* UNDEF accesses to D16-D31 if they don't exist. */
- if (!dc_isar_feature(aa32_simd_r32, s) && (vd & 0x10)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
+ /* UNDEF accesses to D16-D31 if they don't exist. */
+ if (!dc_isar_feature(aa32_simd_r32, s) && (vd & 0x10)) {
return false;
}
@@ -2060,6 +2062,10 @@ static bool trans_VCMP_dp(DisasContext *s, arg_VCMP_dp
*a)
{
TCGv_i64 vd, vm;
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
+ return false;
+ }
+
/* Vm/M bits must be zero for the Z variant */
if (a->z && a->vm != 0) {
return false;
@@ -2070,10 +2076,6 @@ static bool trans_VCMP_dp(DisasContext *s, arg_VCMP_dp
*a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
- return false;
- }
-
if (!vfp_access_check(s)) {
return true;
}
@@ -2134,6 +2136,10 @@ static bool trans_VCVT_f64_f16(DisasContext *s,
arg_VCVT_f64_f16 *a)
TCGv_i32 tmp;
TCGv_i64 vd;
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
+ return false;
+ }
+
if (!dc_isar_feature(aa32_fp16_dpconv, s)) {
return false;
}
@@ -2143,10 +2149,6 @@ static bool trans_VCVT_f64_f16(DisasContext *s,
arg_VCVT_f64_f16 *a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
- return false;
- }
-
if (!vfp_access_check(s)) {
return true;
}
@@ -2200,6 +2202,10 @@ static bool trans_VCVT_f16_f64(DisasContext *s,
arg_VCVT_f16_f64 *a)
TCGv_i32 tmp;
TCGv_i64 vm;
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
+ return false;
+ }
+
if (!dc_isar_feature(aa32_fp16_dpconv, s)) {
return false;
}
@@ -2209,10 +2215,6 @@ static bool trans_VCVT_f16_f64(DisasContext *s,
arg_VCVT_f16_f64 *a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
- return false;
- }
-
if (!vfp_access_check(s)) {
return true;
}
@@ -2260,6 +2262,10 @@ static bool trans_VRINTR_dp(DisasContext *s,
arg_VRINTR_dp *a)
TCGv_ptr fpst;
TCGv_i64 tmp;
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
+ return false;
+ }
+
if (!dc_isar_feature(aa32_vrint, s)) {
return false;
}
@@ -2269,10 +2275,6 @@ static bool trans_VRINTR_dp(DisasContext *s,
arg_VRINTR_dp *a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
- return false;
- }
-
if (!vfp_access_check(s)) {
return true;
}
@@ -2321,6 +2323,10 @@ static bool trans_VRINTZ_dp(DisasContext *s,
arg_VRINTZ_dp *a)
TCGv_i64 tmp;
TCGv_i32 tcg_rmode;
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
+ return false;
+ }
+
if (!dc_isar_feature(aa32_vrint, s)) {
return false;
}
@@ -2330,10 +2336,6 @@ static bool trans_VRINTZ_dp(DisasContext *s,
arg_VRINTZ_dp *a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
- return false;
- }
-
if (!vfp_access_check(s)) {
return true;
}
@@ -2380,6 +2382,10 @@ static bool trans_VRINTX_dp(DisasContext *s,
arg_VRINTX_dp *a)
TCGv_ptr fpst;
TCGv_i64 tmp;
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
+ return false;
+ }
+
if (!dc_isar_feature(aa32_vrint, s)) {
return false;
}
@@ -2389,10 +2395,6 @@ static bool trans_VRINTX_dp(DisasContext *s,
arg_VRINTX_dp *a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
- return false;
- }
-
if (!vfp_access_check(s)) {
return true;
}
@@ -2412,12 +2414,12 @@ static bool trans_VCVT_sp(DisasContext *s, arg_VCVT_sp
*a)
TCGv_i64 vd;
TCGv_i32 vm;
- /* UNDEF accesses to D16-D31 if they don't exist. */
- if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
+ /* UNDEF accesses to D16-D31 if they don't exist. */
+ if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) {
return false;
}
@@ -2440,12 +2442,12 @@ static bool trans_VCVT_dp(DisasContext *s, arg_VCVT_dp
*a)
TCGv_i64 vm;
TCGv_i32 vd;
- /* UNDEF accesses to D16-D31 if they don't exist. */
- if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
+ /* UNDEF accesses to D16-D31 if they don't exist. */
+ if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) {
return false;
}
@@ -2494,12 +2496,12 @@ static bool trans_VCVT_int_dp(DisasContext *s,
arg_VCVT_int_dp *a)
TCGv_i64 vd;
TCGv_ptr fpst;
- /* UNDEF accesses to D16-D31 if they don't exist. */
- if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
+ /* UNDEF accesses to D16-D31 if they don't exist. */
+ if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) {
return false;
}
@@ -2530,6 +2532,10 @@ static bool trans_VJCVT(DisasContext *s, arg_VJCVT *a)
TCGv_i32 vd;
TCGv_i64 vm;
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
+ return false;
+ }
+
if (!dc_isar_feature(aa32_jscvt, s)) {
return false;
}
@@ -2539,10 +2545,6 @@ static bool trans_VJCVT(DisasContext *s, arg_VJCVT *a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
- return false;
- }
-
if (!vfp_access_check(s)) {
return true;
}
@@ -2623,6 +2625,10 @@ static bool trans_VCVT_fix_dp(DisasContext *s,
arg_VCVT_fix_dp *a)
TCGv_ptr fpst;
int frac_bits;
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
+ return false;
+ }
+
if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) {
return false;
}
@@ -2632,10 +2638,6 @@ static bool trans_VCVT_fix_dp(DisasContext *s,
arg_VCVT_fix_dp *a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
- return false;
- }
-
if (!vfp_access_check(s)) {
return true;
}
@@ -2723,12 +2725,12 @@ static bool trans_VCVT_dp_int(DisasContext *s,
arg_VCVT_dp_int *a)
TCGv_i64 vm;
TCGv_ptr fpst;
- /* UNDEF accesses to D16-D31 if they don't exist. */
- if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
+ /* UNDEF accesses to D16-D31 if they don't exist. */
+ if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) {
return false;
}
--
2.20.1
- [PATCH v2 00/17] target/arm: vfp feature and decodetree cleanup, Richard Henderson, 2020/02/24
- [PATCH v2 02/17] target/arm: Rename isar_feature_aa32_fpdp_v2, Richard Henderson, 2020/02/24
- [PATCH v2 03/17] target/arm: Add isar_feature_aa32_{fpsp_v2, fpsp_v3, fpdp_v3}, Richard Henderson, 2020/02/24
- [PATCH v2 01/17] target/arm: Add isar_feature_aa32_vfp_simd, Richard Henderson, 2020/02/24
- [PATCH v2 05/17] target/arm: Improve ID_AA64PFR0 FP/SIMD validation, Richard Henderson, 2020/02/24
- [PATCH v2 04/17] target/arm: Add isar_feature_aa64_fp_simd, isar_feature_aa32_vfp, Richard Henderson, 2020/02/24
- [PATCH v2 07/17] target/arm: Replace ARM_FEATURE_VFP3 checks with fp{sp, dp}_v3, Richard Henderson, 2020/02/24
- [PATCH v2 06/17] target/arm: Perform fpdp_v2 check first,
Richard Henderson <=
- [PATCH v2 08/17] target/arm: Add missing checks for fpsp_v2, Richard Henderson, 2020/02/24
- [PATCH v2 09/17] target/arm: Replace ARM_FEATURE_VFP4 with isar_feature_aa32_simdfmac, Richard Henderson, 2020/02/24
- [PATCH v2 10/17] target/arm: Remove ARM_FEATURE_VFP check from disas_vfp_insn, Richard Henderson, 2020/02/24
- [PATCH v2 11/17] target/arm: Move VLLDM and VLSTM to vfp.decode, Richard Henderson, 2020/02/24
- [PATCH v2 12/17] target/arm: Move the vfp decodetree calls next to the base isa, Richard Henderson, 2020/02/24
- [PATCH v2 13/17] linux-user/arm: Replace ARM_FEATURE_VFP* tests for HWCAP, Richard Henderson, 2020/02/24