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[PATCH v2 12/17] target/arm: Move the vfp decodetree calls next to the b
From: |
Richard Henderson |
Subject: |
[PATCH v2 12/17] target/arm: Move the vfp decodetree calls next to the base isa |
Date: |
Mon, 24 Feb 2020 14:22:27 -0800 |
Have the calls adjacent as an intermediate step toward
actually merging the decodes.
Signed-off-by: Richard Henderson <address@hidden>
---
v2: Fix fallthrough in disas_arm_insn vs vfp insns.
---
target/arm/translate.c | 83 +++++++++++++++---------------------------
1 file changed, 29 insertions(+), 54 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 5b7cad1ea2..6259064ea7 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -2646,31 +2646,6 @@ static void gen_neon_dup_high16(TCGv_i32 var)
tcg_temp_free_i32(tmp);
}
-/*
- * Disassemble a VFP instruction. Returns nonzero if an error occurred
- * (ie. an undefined instruction).
- */
-static int disas_vfp_insn(DisasContext *s, uint32_t insn)
-{
- /*
- * If the decodetree decoder handles this insn it will always
- * emit code to either execute the insn or generate an appropriate
- * exception; so we don't need to ever return non-zero to tell
- * the calling code to emit an UNDEF exception.
- */
- if (extract32(insn, 28, 4) == 0xf) {
- if (disas_vfp_uncond(s, insn)) {
- return 0;
- }
- } else {
- if (disas_vfp(s, insn)) {
- return 0;
- }
- }
- /* If the decodetree decoder didn't handle this insn, it must be UNDEF */
- return 1;
-}
-
static inline bool use_goto_tb(DisasContext *s, target_ulong dest)
{
#ifndef CONFIG_USER_ONLY
@@ -10778,7 +10753,9 @@ static void disas_arm_insn(DisasContext *s, unsigned
int insn)
ARCH(5);
/* Unconditional instructions. */
- if (disas_a32_uncond(s, insn)) {
+ /* TODO: Perhaps merge these into one decodetree output file. */
+ if (disas_a32_uncond(s, insn) ||
+ disas_vfp_uncond(s, insn)) {
return;
}
/* fall back to legacy decoder */
@@ -10805,13 +10782,6 @@ static void disas_arm_insn(DisasContext *s, unsigned
int insn)
}
return;
}
- if ((insn & 0x0f000e10) == 0x0e000a00) {
- /* VFP. */
- if (disas_vfp_insn(s, insn)) {
- goto illegal_op;
- }
- return;
- }
if ((insn & 0x0e000f00) == 0x0c000100) {
if (arm_dc_feature(s, ARM_FEATURE_IWMMXT)) {
/* iWMMXt register transfer. */
@@ -10842,7 +10812,9 @@ static void disas_arm_insn(DisasContext *s, unsigned
int insn)
arm_skip_unless(s, cond);
}
- if (disas_a32(s, insn)) {
+ /* TODO: Perhaps merge these into one decodetree output file. */
+ if (disas_a32(s, insn) ||
+ disas_vfp(s, insn)) {
return;
}
/* fall back to legacy decoder */
@@ -10852,11 +10824,10 @@ static void disas_arm_insn(DisasContext *s, unsigned
int insn)
case 0xd:
case 0xe:
if (((insn >> 8) & 0xe) == 10) {
- /* VFP. */
- if (disas_vfp_insn(s, insn)) {
- goto illegal_op;
- }
- } else if (disas_coproc_insn(s, insn)) {
+ /* VFP, but failed disas_vfp. */
+ goto illegal_op;
+ }
+ if (disas_coproc_insn(s, insn)) {
/* Coprocessor. */
goto illegal_op;
}
@@ -10945,7 +10916,14 @@ static void disas_thumb2_insn(DisasContext *s,
uint32_t insn)
ARCH(6T2);
}
- if (disas_t32(s, insn)) {
+ /*
+ * TODO: Perhaps merge these into one decodetree output file.
+ * Note disas_vfp is written for a32 with cond field in the
+ * top nibble. The t32 encoding requires 0xe in the top nibble.
+ */
+ if (disas_t32(s, insn) ||
+ disas_vfp_uncond(s, insn) ||
+ ((insn >> 28) == 0xe && disas_vfp(s, insn))) {
return;
}
/* fall back to legacy decoder */
@@ -10962,17 +10940,15 @@ static void disas_thumb2_insn(DisasContext *s,
uint32_t insn)
goto illegal_op; /* op0 = 0b11 : unallocated */
}
- if (disas_vfp_insn(s, insn)) {
- if (((insn >> 8) & 0xe) == 10 &&
- dc_isar_feature(aa32_fpsp_v2, s)) {
- /* FP, and the CPU supports it */
- goto illegal_op;
- } else {
- /* All other insns: NOCP */
- gen_exception_insn(s, s->pc_curr, EXCP_NOCP,
- syn_uncategorized(),
- default_exception_el(s));
- }
+ if (((insn >> 8) & 0xe) == 10 &&
+ dc_isar_feature(aa32_fpsp_v2, s)) {
+ /* FP, and the CPU supports it */
+ goto illegal_op;
+ } else {
+ /* All other insns: NOCP */
+ gen_exception_insn(s, s->pc_curr, EXCP_NOCP,
+ syn_uncategorized(),
+ default_exception_el(s));
}
break;
}
@@ -10995,9 +10971,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t
insn)
goto illegal_op;
}
} else if (((insn >> 8) & 0xe) == 10) {
- if (disas_vfp_insn(s, insn)) {
- goto illegal_op;
- }
+ /* VFP, but failed disas_vfp. */
+ goto illegal_op;
} else {
if (insn & (1 << 28))
goto illegal_op;
--
2.20.1
- [PATCH v2 04/17] target/arm: Add isar_feature_aa64_fp_simd, isar_feature_aa32_vfp, (continued)
- [PATCH v2 04/17] target/arm: Add isar_feature_aa64_fp_simd, isar_feature_aa32_vfp, Richard Henderson, 2020/02/24
- [PATCH v2 07/17] target/arm: Replace ARM_FEATURE_VFP3 checks with fp{sp, dp}_v3, Richard Henderson, 2020/02/24
- [PATCH v2 06/17] target/arm: Perform fpdp_v2 check first, Richard Henderson, 2020/02/24
- [PATCH v2 08/17] target/arm: Add missing checks for fpsp_v2, Richard Henderson, 2020/02/24
- [PATCH v2 09/17] target/arm: Replace ARM_FEATURE_VFP4 with isar_feature_aa32_simdfmac, Richard Henderson, 2020/02/24
- [PATCH v2 10/17] target/arm: Remove ARM_FEATURE_VFP check from disas_vfp_insn, Richard Henderson, 2020/02/24
- [PATCH v2 11/17] target/arm: Move VLLDM and VLSTM to vfp.decode, Richard Henderson, 2020/02/24
- [PATCH v2 12/17] target/arm: Move the vfp decodetree calls next to the base isa,
Richard Henderson <=
- [PATCH v2 13/17] linux-user/arm: Replace ARM_FEATURE_VFP* tests for HWCAP, Richard Henderson, 2020/02/24
- [PATCH v2 14/17] target/arm: Remove ARM_FEATURE_VFP*, Richard Henderson, 2020/02/24
- [PATCH v2 16/17] target/arm: Split VFM decode, Richard Henderson, 2020/02/24
- [PATCH v2 15/17] target/arm: Add formats for some vfp 2 and 3-register insns, Richard Henderson, 2020/02/24
- [PATCH v2 17/17] target/arm: Split VMINMAXNM decode, Richard Henderson, 2020/02/24
- Re: [PATCH v2 00/17] target/arm: vfp feature and decodetree cleanup, Peter Maydell, 2020/02/25