[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[RFC PATCH v2 27/67] Hexagon generator phase 2 - printinsn-generated.h
From: |
Taylor Simpson |
Subject: |
[RFC PATCH v2 27/67] Hexagon generator phase 2 - printinsn-generated.h |
Date: |
Fri, 28 Feb 2020 10:43:23 -0600 |
Data for printing (disassembling) each instruction (format string + operands)
Signed-off-by: Taylor Simpson <address@hidden>
---
target/hexagon/do_qemu.py | 151 ++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 151 insertions(+)
diff --git a/target/hexagon/do_qemu.py b/target/hexagon/do_qemu.py
index 0c7643a..32543c8 100755
--- a/target/hexagon/do_qemu.py
+++ b/target/hexagon/do_qemu.py
@@ -892,3 +892,154 @@ realf.write(f.getvalue())
realf.close()
f.close()
+##
+## Generate the printinsn_generated.h file
+## Data for printing each instruction (format string + operands)
+##
+def regprinter(m):
+ str = m.group(1)
+ str += ":".join(["%d"]*len(m.group(2)))
+ str += m.group(3)
+ if ('S' in m.group(1)) and (len(m.group(2)) == 1):
+ str += "/%s"
+ elif ('C' in m.group(1)) and (len(m.group(2)) == 1):
+ str += "/%s"
+ return str
+
+# Regular expression that matches any operator that contains '=' character:
+opswithequal_re = '[-+^&|!<>=]?='
+# Regular expression that matches any assignment operator.
+assignment_re = '[-+^&|]?='
+
+# Out of the operators that contain the = sign, if the operator is also an
+# assignment, spaces will be added around it, unless it's enclosed within
+# parentheses, or spaces are already present.
+
+equals = re.compile(opswithequal_re)
+assign = re.compile(assignment_re)
+
+def spacify(s):
+ slen = len(s)
+ paren_count = {}
+ i = 0
+ pc = 0
+ while i < slen:
+ c = s[i]
+ if c == '(':
+ pc += 1
+ elif c == ')':
+ pc -= 1
+ paren_count[i] = pc
+ i += 1
+
+ # Iterate over all operators that contain the equal sign. If any
+ # match is also an assignment operator, add spaces around it if
+ # the parenthesis count is 0.
+ pos = 0
+ out = []
+ for m in equals.finditer(s):
+ ms = m.start()
+ me = m.end()
+ # t is the string that matched opswithequal_re.
+ t = m.string[ms:me]
+ out += s[pos:ms]
+ pos = me
+ if paren_count[ms] == 0:
+ # Check if the entire string t is an assignment.
+ am = assign.match(t)
+ if am and len(am.group(0)) == me-ms:
+ # Don't add spaces if they are already there.
+ if ms > 0 and s[ms-1] != ' ':
+ out.append(' ')
+ out += t
+ if me < slen and s[me] != ' ':
+ out.append(' ')
+ continue
+ # If this is not an assignment, just append it to the output
+ # string.
+ out += t
+
+ # Append the remaining part of the string.
+ out += s[pos:len(s)]
+ return ''.join(out)
+
+immext_casere = re.compile(r'IMMEXT\(([A-Za-z])')
+
+f = StringIO()
+
+for tag in tags:
+ if not behdict[tag]: continue
+ extendable_upper_imm = False
+ extendable_lower_imm = False
+ m = immext_casere.search(semdict[tag])
+ if m:
+ if m.group(1).isupper():
+ extendable_upper_imm = True
+ else:
+ extendable_lower_imm = True
+ beh = behdict[tag]
+ beh = regre.sub(regprinter,beh)
+ beh = absimmre.sub(r"#%s0x%x",beh)
+ beh = relimmre.sub(r"PC+%s%d",beh)
+ beh = spacify(beh)
+ # Print out a literal "%s" at the end, used to match empty string
+ # so C won't complain at us
+ if ("A_VECX" in attribdict[tag]): macname = "DEF_VECX_PRINTINFO"
+ else: macname = "DEF_PRINTINFO"
+ f.write('%s(%s,"%s%%s"' % (macname,tag,beh))
+ regs_or_imms = reg_or_immre.findall(behdict[tag])
+ ri = 0
+ seenregs = {}
+ for allregs,a,b,c,d,allimm,immlett,bits,immshift in regs_or_imms:
+ if a:
+ #register
+ if b in seenregs:
+ regno = seenregs[b]
+ else:
+ regno = ri
+ if len(b) == 1:
+ f.write(',REGNO(%d)' % regno)
+ if 'S' in a:
+ f.write(',sreg2str(REGNO(%d))' % regno)
+ elif 'C' in a:
+ f.write(',creg2str(REGNO(%d))' % regno)
+ elif len(b) == 2:
+ f.write(',REGNO(%d)+1,REGNO(%d)' % (regno,regno))
+ elif len(b) == 4:
+ f.write(',REGNO(%d)^3,REGNO(%d)^2,REGNO(%d)^1,REGNO(%d)' % \
+ (regno,regno,regno,regno))
+ else:
+ print("Put some stuff to handle quads here")
+ if b not in seenregs:
+ seenregs[b] = ri
+ ri += 1
+ else:
+ #immediate
+ if (immlett.isupper()):
+ if extendable_upper_imm:
+ if immlett in 'rR':
+ f.write(',insn->extension_valid?"##":""')
+ else:
+ f.write(',insn->extension_valid?"#":""')
+ else:
+ f.write(',""')
+ ii = 1
+ else:
+ if extendable_lower_imm:
+ if immlett in 'rR':
+ f.write(',insn->extension_valid?"##":""')
+ else:
+ f.write(',insn->extension_valid?"#":""')
+ else:
+ f.write(',""')
+ ii = 0
+ f.write(',IMMNO(%d)' % ii)
+ # append empty string so there is at least one more arg
+ f.write(',"")\n')
+
+realf = open('printinsn_generated.h','w')
+realf.write(f.getvalue())
+realf.close()
+f.close()
+
+
--
2.7.4
- [RFC PATCH v2 17/67] Hexagon arch import - macro definitions, (continued)
- [RFC PATCH v2 17/67] Hexagon arch import - macro definitions, Taylor Simpson, 2020/02/28
- [RFC PATCH v2 20/67] Hexagon instruction utility functions, Taylor Simpson, 2020/02/28
- [RFC PATCH v2 24/67] Hexagon generator phase 2 - opcodes_def_generated.h, Taylor Simpson, 2020/02/28
- [RFC PATCH v2 04/67] Hexagon CPU Scalar Core Definition, Taylor Simpson, 2020/02/28
- [RFC PATCH v2 11/67] Hexagon register fields, Taylor Simpson, 2020/02/28
- [RFC PATCH v2 01/67] Hexagon Maintainers, Taylor Simpson, 2020/02/28
- [RFC PATCH v2 08/67] Hexagon GDB Stub, Taylor Simpson, 2020/02/28
- [RFC PATCH v2 10/67] Hexagon instruction and packet types, Taylor Simpson, 2020/02/28
- [RFC PATCH v2 03/67] Hexagon ELF Machine Definition, Taylor Simpson, 2020/02/28
- [RFC PATCH v2 21/67] Hexagon generator phase 1 - C preprocessor for semantics, Taylor Simpson, 2020/02/28
- [RFC PATCH v2 27/67] Hexagon generator phase 2 - printinsn-generated.h,
Taylor Simpson <=
- [RFC PATCH v2 19/67] Hexagon instruction class definitions, Taylor Simpson, 2020/02/28
- [RFC PATCH v2 07/67] Hexagon CPU Scalar Core Helpers, Taylor Simpson, 2020/02/28
- [RFC PATCH v2 13/67] Hexagon register map, Taylor Simpson, 2020/02/28
- [RFC PATCH v2 02/67] Hexagon README, Taylor Simpson, 2020/02/28
- [RFC PATCH v2 23/67] Hexagon generator phase 2 - qemu_wrap_generated.h, Taylor Simpson, 2020/02/28
- [RFC PATCH v2 25/67] Hexagon generator phase 2 - op_attribs_generated.h, Taylor Simpson, 2020/02/28
- [RFC PATCH v2 29/67] Hexagon generater phase 4 - Decode tree, Taylor Simpson, 2020/02/28
- [RFC PATCH v2 18/67] Hexagon arch import - instruction encoding, Taylor Simpson, 2020/02/28
- [RFC PATCH v2 44/67] Hexagon TCG generation - step 06, Taylor Simpson, 2020/02/28
- [RFC PATCH v2 31/67] Hexagon macros to interface with the generator, Taylor Simpson, 2020/02/28