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[PULL v2 07/20] target/riscv: check before allocating TCG temps
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From: |
Alistair Francis |
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Subject: |
[PULL v2 07/20] target/riscv: check before allocating TCG temps |
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Date: |
Fri, 14 Aug 2020 08:04:53 -0700 |
From: LIU Zhiwei <zhiwei_liu@c-sky.com>
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200626205917.4545-5-zhiwei_liu@c-sky.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200724002807.441147-8-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn_trans/trans_rvd.inc.c | 8 ++++----
target/riscv/insn_trans/trans_rvf.inc.c | 8 ++++----
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvd.inc.c
b/target/riscv/insn_trans/trans_rvd.inc.c
index ea1044f13b..4f832637fa 100644
--- a/target/riscv/insn_trans/trans_rvd.inc.c
+++ b/target/riscv/insn_trans/trans_rvd.inc.c
@@ -20,10 +20,10 @@
static bool trans_fld(DisasContext *ctx, arg_fld *a)
{
- TCGv t0 = tcg_temp_new();
- gen_get_gpr(t0, a->rs1);
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVD);
+ TCGv t0 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
tcg_gen_addi_tl(t0, t0, a->imm);
tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEQ);
@@ -35,10 +35,10 @@ static bool trans_fld(DisasContext *ctx, arg_fld *a)
static bool trans_fsd(DisasContext *ctx, arg_fsd *a)
{
- TCGv t0 = tcg_temp_new();
- gen_get_gpr(t0, a->rs1);
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVD);
+ TCGv t0 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
tcg_gen_addi_tl(t0, t0, a->imm);
tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEQ);
diff --git a/target/riscv/insn_trans/trans_rvf.inc.c
b/target/riscv/insn_trans/trans_rvf.inc.c
index 138e317723..3dfec8211d 100644
--- a/target/riscv/insn_trans/trans_rvf.inc.c
+++ b/target/riscv/insn_trans/trans_rvf.inc.c
@@ -25,10 +25,10 @@
static bool trans_flw(DisasContext *ctx, arg_flw *a)
{
- TCGv t0 = tcg_temp_new();
- gen_get_gpr(t0, a->rs1);
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
+ TCGv t0 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
tcg_gen_addi_tl(t0, t0, a->imm);
tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEUL);
@@ -41,11 +41,11 @@ static bool trans_flw(DisasContext *ctx, arg_flw *a)
static bool trans_fsw(DisasContext *ctx, arg_fsw *a)
{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVF);
TCGv t0 = tcg_temp_new();
gen_get_gpr(t0, a->rs1);
- REQUIRE_FPU;
- REQUIRE_EXT(ctx, RVF);
tcg_gen_addi_tl(t0, t0, a->imm);
tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEUL);
--
2.27.0
- [PULL v2 00/20] riscv-to-apply queue, Alistair Francis, 2020/08/14
- [PULL v2 03/20] target/riscv: Generate nanboxed results from trans_rvf.inc.c, Alistair Francis, 2020/08/14
- [PULL v2 15/20] gitlab-ci/opensbi: Update GitLab CI to build generic platform, Alistair Francis, 2020/08/14
- [PULL v2 02/20] target/riscv: Generalize gen_nanbox_fpr to gen_nanbox_s, Alistair Francis, 2020/08/14
- [PULL v2 04/20] target/riscv: Check nanboxed inputs to fp helpers, Alistair Francis, 2020/08/14
- [PULL v2 01/20] target/riscv: Generate nanboxed results from fp helpers, Alistair Francis, 2020/08/14
- [PULL v2 05/20] target/riscv: Check nanboxed inputs in trans_rvf.inc.c, Alistair Francis, 2020/08/14
- [PULL v2 16/20] target/riscv: Fix the translation of physical address, Alistair Francis, 2020/08/14
- [PULL v2 06/20] target/riscv: Clean up fmv.w.x, Alistair Francis, 2020/08/14
- [PULL v2 07/20] target/riscv: check before allocating TCG temps,
Alistair Francis <=
- [PULL v2 17/20] target/riscv: Change the TLB page size depends on PMP entries., Alistair Francis, 2020/08/14
- [PULL v2 08/20] hw/riscv: sifive_u: Add a dummy L2 cache controller device, Alistair Francis, 2020/08/14
- [PULL v2 09/20] riscv: Fix bug in setting pmpcfg CSR for RISCV64, Alistair Francis, 2020/08/14
- [PULL v2 18/20] hw/intc: ibex_plic: Update the pending irqs, Alistair Francis, 2020/08/14
- [PULL v2 20/20] hw/intc: ibex_plic: Honour source priorities, Alistair Francis, 2020/08/14
- [PULL v2 19/20] hw/intc: ibex_plic: Don't allow repeat interrupts on claimed lines, Alistair Francis, 2020/08/14
- [PULL v2 10/20] configure: Create symbolic links for pc-bios/*.elf files, Alistair Francis, 2020/08/14
- [PULL v2 11/20] roms/opensbi: Upgrade from v0.7 to v0.8, Alistair Francis, 2020/08/14
- [PULL v2 12/20] roms/Makefile: Build the generic platform for RISC-V OpenSBI firmware, Alistair Francis, 2020/08/14
- [PULL v2 13/20] hw/riscv: Use pre-built bios image of generic platform for virt & sifive_u, Alistair Francis, 2020/08/14