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[PULL v2 19/20] hw/intc: ibex_plic: Don't allow repeat interrupts on cla
From: |
Alistair Francis |
Subject: |
[PULL v2 19/20] hw/intc: ibex_plic: Don't allow repeat interrupts on claimed lines |
Date: |
Fri, 14 Aug 2020 08:05:05 -0700 |
Once an interrupt has been claimed, but before it has been compelted we
shouldn't receive any more pending interrupts. This patche keeps track
of this to ensure that we don't see any more interrupts until it is
completed.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id:
<394c3f070615ff2b4fab61a1cf9cb48c122913b7.1595655188.git.alistair.francis@wdc.com>
---
include/hw/intc/ibex_plic.h | 1 +
hw/intc/ibex_plic.c | 17 +++++++++++++++++
2 files changed, 18 insertions(+)
diff --git a/include/hw/intc/ibex_plic.h b/include/hw/intc/ibex_plic.h
index ddc7909903..d8eb09b258 100644
--- a/include/hw/intc/ibex_plic.h
+++ b/include/hw/intc/ibex_plic.h
@@ -33,6 +33,7 @@ typedef struct IbexPlicState {
MemoryRegion mmio;
uint32_t *pending;
+ uint32_t *claimed;
uint32_t *source;
uint32_t *priority;
uint32_t *enable;
diff --git a/hw/intc/ibex_plic.c b/hw/intc/ibex_plic.c
index 578edd2ce0..669247ef08 100644
--- a/hw/intc/ibex_plic.c
+++ b/hw/intc/ibex_plic.c
@@ -43,6 +43,14 @@ static void ibex_plic_irqs_set_pending(IbexPlicState *s, int
irq, bool level)
{
int pending_num = irq / 32;
+ if (s->claimed[pending_num] & 1 << (irq % 32)) {
+ /*
+ * The interrupt has been claimed, but not compelted.
+ * The pending bit can't be set.
+ */
+ return;
+ }
+
s->pending[pending_num] |= level << (irq % 32);
}
@@ -120,6 +128,10 @@ static uint64_t ibex_plic_read(void *opaque, hwaddr addr,
int pending_num = s->claim / 32;
s->pending[pending_num] &= ~(1 << (s->claim % 32));
+ /* Set the interrupt as claimed, but not compelted */
+ s->claimed[pending_num] |= 1 << (s->claim % 32);
+
+ /* Return the current claimed interrupt */
ret = s->claim;
/* Update the interrupt status after the claim */
@@ -155,6 +167,10 @@ static void ibex_plic_write(void *opaque, hwaddr addr,
/* Interrupt was completed */
s->claim = 0;
}
+ if (s->claimed[value / 32] & 1 << (value % 32)) {
+ /* This value was already claimed, clear it. */
+ s->claimed[value / 32] &= ~(1 << (value % 32));
+ }
}
ibex_plic_update(s);
@@ -215,6 +231,7 @@ static void ibex_plic_realize(DeviceState *dev, Error
**errp)
int i;
s->pending = g_new0(uint32_t, s->pending_num);
+ s->claimed = g_new0(uint32_t, s->pending_num);
s->source = g_new0(uint32_t, s->source_num);
s->priority = g_new0(uint32_t, s->priority_num);
s->enable = g_new0(uint32_t, s->enable_num);
--
2.27.0
- [PULL v2 01/20] target/riscv: Generate nanboxed results from fp helpers, (continued)
- [PULL v2 01/20] target/riscv: Generate nanboxed results from fp helpers, Alistair Francis, 2020/08/14
- [PULL v2 05/20] target/riscv: Check nanboxed inputs in trans_rvf.inc.c, Alistair Francis, 2020/08/14
- [PULL v2 16/20] target/riscv: Fix the translation of physical address, Alistair Francis, 2020/08/14
- [PULL v2 06/20] target/riscv: Clean up fmv.w.x, Alistair Francis, 2020/08/14
- [PULL v2 07/20] target/riscv: check before allocating TCG temps, Alistair Francis, 2020/08/14
- [PULL v2 17/20] target/riscv: Change the TLB page size depends on PMP entries., Alistair Francis, 2020/08/14
- [PULL v2 08/20] hw/riscv: sifive_u: Add a dummy L2 cache controller device, Alistair Francis, 2020/08/14
- [PULL v2 09/20] riscv: Fix bug in setting pmpcfg CSR for RISCV64, Alistair Francis, 2020/08/14
- [PULL v2 18/20] hw/intc: ibex_plic: Update the pending irqs, Alistair Francis, 2020/08/14
- [PULL v2 20/20] hw/intc: ibex_plic: Honour source priorities, Alistair Francis, 2020/08/14
- [PULL v2 19/20] hw/intc: ibex_plic: Don't allow repeat interrupts on claimed lines,
Alistair Francis <=
- [PULL v2 10/20] configure: Create symbolic links for pc-bios/*.elf files, Alistair Francis, 2020/08/14
- [PULL v2 11/20] roms/opensbi: Upgrade from v0.7 to v0.8, Alistair Francis, 2020/08/14
- [PULL v2 12/20] roms/Makefile: Build the generic platform for RISC-V OpenSBI firmware, Alistair Francis, 2020/08/14
- [PULL v2 13/20] hw/riscv: Use pre-built bios image of generic platform for virt & sifive_u, Alistair Francis, 2020/08/14
- [PULL v2 14/20] hw/riscv: spike: Change the default bios to use generic platform image, Alistair Francis, 2020/08/14
- Re: [PULL v2 00/20] riscv-to-apply queue, Peter Maydell, 2020/08/21