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[PULL v2 09/20] riscv: Fix bug in setting pmpcfg CSR for RISCV64
From: |
Alistair Francis |
Subject: |
[PULL v2 09/20] riscv: Fix bug in setting pmpcfg CSR for RISCV64 |
Date: |
Fri, 14 Aug 2020 08:04:55 -0700 |
From: Hou Weiying <weiying_hou@outlook.com>
First, sizeof(target_ulong) equals to 4 on riscv32, so this change
does not change the function on riscv32. Second, sizeof(target_ulong)
equals to 8 on riscv64, and 'reg_index * 8 + i' is not a legal
pmp_index (we will explain later), which should be 'reg_index * 4 + i'.
If the parameter reg_index equals to 2 (means that we will change the
value of pmpcfg2, or the second pmpcfg on riscv64), then
pmpcfg_csr_write(env, 2, val) will map write tasks to
pmp_write_cfg(env, 2 * 8 + [0...7], val). However, no cfg csr is indexed
by value 16 or 23 on riscv64, so we consider it as a bug.
We are looking for constant (e.g., define a new constant named
RISCV_WORD_SIZE) in QEMU to help others understand code better,
but none was found. A possible good explanation of this literal is it is
the minimum word length on riscv is 4 bytes (32 bit).
Signed-off-by: Hongzheng-Li <Ethan.Lee.QNL@gmail.com>
Signed-off-by: Hou Weiying <weiying_hou@outlook.com>
Signed-off-by: Myriad-Dreamin <camiyoru@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id:
<SG2PR02MB263420036254AC8841F66CE393460@SG2PR02MB2634.apcprd02.prod.outlook.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/pmp.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 2a2b9f5363..b14feeb7da 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -320,8 +320,7 @@ void pmpcfg_csr_write(CPURISCVState *env, uint32_t
reg_index,
for (i = 0; i < sizeof(target_ulong); i++) {
cfg_val = (val >> 8 * i) & 0xff;
- pmp_write_cfg(env, (reg_index * sizeof(target_ulong)) + i,
- cfg_val);
+ pmp_write_cfg(env, (reg_index * 4) + i, cfg_val);
}
}
@@ -336,7 +335,7 @@ target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32_t
reg_index)
target_ulong val = 0;
for (i = 0; i < sizeof(target_ulong); i++) {
- val = pmp_read_cfg(env, (reg_index * sizeof(target_ulong)) + i);
+ val = pmp_read_cfg(env, (reg_index * 4) + i);
cfg_val |= (val << (i * 8));
}
trace_pmpcfg_csr_read(env->mhartid, reg_index, cfg_val);
--
2.27.0
- [PULL v2 15/20] gitlab-ci/opensbi: Update GitLab CI to build generic platform, (continued)
- [PULL v2 15/20] gitlab-ci/opensbi: Update GitLab CI to build generic platform, Alistair Francis, 2020/08/14
- [PULL v2 02/20] target/riscv: Generalize gen_nanbox_fpr to gen_nanbox_s, Alistair Francis, 2020/08/14
- [PULL v2 04/20] target/riscv: Check nanboxed inputs to fp helpers, Alistair Francis, 2020/08/14
- [PULL v2 01/20] target/riscv: Generate nanboxed results from fp helpers, Alistair Francis, 2020/08/14
- [PULL v2 05/20] target/riscv: Check nanboxed inputs in trans_rvf.inc.c, Alistair Francis, 2020/08/14
- [PULL v2 16/20] target/riscv: Fix the translation of physical address, Alistair Francis, 2020/08/14
- [PULL v2 06/20] target/riscv: Clean up fmv.w.x, Alistair Francis, 2020/08/14
- [PULL v2 07/20] target/riscv: check before allocating TCG temps, Alistair Francis, 2020/08/14
- [PULL v2 17/20] target/riscv: Change the TLB page size depends on PMP entries., Alistair Francis, 2020/08/14
- [PULL v2 08/20] hw/riscv: sifive_u: Add a dummy L2 cache controller device, Alistair Francis, 2020/08/14
- [PULL v2 09/20] riscv: Fix bug in setting pmpcfg CSR for RISCV64,
Alistair Francis <=
- [PULL v2 18/20] hw/intc: ibex_plic: Update the pending irqs, Alistair Francis, 2020/08/14
- [PULL v2 20/20] hw/intc: ibex_plic: Honour source priorities, Alistair Francis, 2020/08/14
- [PULL v2 19/20] hw/intc: ibex_plic: Don't allow repeat interrupts on claimed lines, Alistair Francis, 2020/08/14
- [PULL v2 10/20] configure: Create symbolic links for pc-bios/*.elf files, Alistair Francis, 2020/08/14
- [PULL v2 11/20] roms/opensbi: Upgrade from v0.7 to v0.8, Alistair Francis, 2020/08/14
- [PULL v2 12/20] roms/Makefile: Build the generic platform for RISC-V OpenSBI firmware, Alistair Francis, 2020/08/14
- [PULL v2 13/20] hw/riscv: Use pre-built bios image of generic platform for virt & sifive_u, Alistair Francis, 2020/08/14
- [PULL v2 14/20] hw/riscv: spike: Change the default bios to use generic platform image, Alistair Francis, 2020/08/14
- Re: [PULL v2 00/20] riscv-to-apply queue, Peter Maydell, 2020/08/21