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Re: [RFC v3 26/71] target/riscv: rvv-1.0: update vext_max_elems() for lo
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From: |
Richard Henderson |
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Subject: |
Re: [RFC v3 26/71] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns |
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Date: |
Fri, 14 Aug 2020 11:36:52 -0700 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 |
On 8/13/20 7:48 PM, Frank Chang wrote:
> esz is passed from e.g. GEN_VEXT_LD_STRIDE() macro:
>
>> #define GEN_VEXT_LD_STRIDE(NAME, ETYPE, LOAD_FN) \
>> void HELPER(NAME)(void *vd, void * v0, target_ulong base, \
>> target_ulong stride, CPURISCVState *env, \
>> uint32_t desc) \
>> { \
>> uint32_t vm = vext_vm(desc); \
>> vext_ldst_stride(vd, v0, base, stride, env, desc, vm, LOAD_FN, \
>> sizeof(ETYPE), GETPC(), MMU_DATA_LOAD); \
>> }
>>
>> GEN_VEXT_LD_STRIDE(vlse8_v, int8_t, lde_b)
>
> which is calculated by sizeof(ETYPE), so the results would be: 1, 2, 4, 8.
> and vext_max_elems() is called by e.g. vext_ldst_stride():
Ah, yes.
>> uint32_t max_elems = vext_max_elems(desc, esz);
>
> I can add another parameter to the macro and pass the hard-coded log2(esz)
> number
> if it's the better way instead of using ctzl().
> Or if there's another approach to get the log2(esz) number more elegantly?
Using ctzl(sizeof(type)) in the GEN_VEXT_LD_STRIDE macro will work well. This
will be constant folded by the compiler.
r~
- Re: [RFC v3 18/71] target/riscv: rvv-1.0: apply nanbox helper in opfvf_trans, (continued)
- [RFC v3 20/71] target/riscv: rvv-1.0: stride load and store instructions, frank . chang, 2020/08/06
- [RFC v3 22/71] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns, frank . chang, 2020/08/06
- [RFC v3 21/71] target/riscv: rvv-1.0: index load and store instructions, frank . chang, 2020/08/06
- [RFC v3 23/71] target/riscv: rvv-1.0: fault-only-first unit stride load, frank . chang, 2020/08/06
- [RFC v3 24/71] target/riscv: rvv-1.0: amo operations, frank . chang, 2020/08/06
- [RFC v3 25/71] target/riscv: rvv-1.0: load/store whole register instructions, frank . chang, 2020/08/06
- [RFC v3 26/71] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns, frank . chang, 2020/08/06
- Re: [RFC v3 26/71] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns, Frank Chang, 2020/08/15
[RFC v3 28/71] target/riscv: rvv-1.0: floating-point square-root instruction, frank . chang, 2020/08/06
[RFC v3 27/71] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation, frank . chang, 2020/08/06
[RFC v3 29/71] target/riscv: rvv-1.0: floating-point classify instructions, frank . chang, 2020/08/06
[RFC v3 32/71] target/riscv: rvv-1.0: set-X-first mask bit instructions, frank . chang, 2020/08/06
[RFC v3 30/71] target/riscv: rvv-1.0: mask population count instruction, frank . chang, 2020/08/06
[RFC v3 31/71] target/riscv: rvv-1.0: find-first-set mask bit instruction, frank . chang, 2020/08/06