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Re: [RFC v3 26/71] target/riscv: rvv-1.0: update vext_max_elems() for lo
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From: |
Richard Henderson |
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Subject: |
Re: [RFC v3 26/71] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns |
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Date: |
Fri, 14 Aug 2020 22:29:17 -0700 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 |
On 8/14/20 7:52 PM, Frank Chang wrote:
> probe_pages(env, base + stride * i, nf * esz, ra, access_type);
> and
> target_ulong addr = base + stride * i + k * esz;
>
> If we pass ctzl(sizeof(type)) in GEN_VEXT_LD_STRIDE(),
> I would still have to do: (1 << esz) to get the correct element size in the
> above calculations.
> Would it eliminate the performance gain we have in vext_max_elems() instead?
Well, no, it will improve performance, because you'll write
addr = base + stride * i + (k << esz)
I.e. strength-reduce the multiply to a shift.
r~
- [RFC v3 22/71] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns, (continued)
- [RFC v3 22/71] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns, frank . chang, 2020/08/06
- [RFC v3 21/71] target/riscv: rvv-1.0: index load and store instructions, frank . chang, 2020/08/06
- [RFC v3 23/71] target/riscv: rvv-1.0: fault-only-first unit stride load, frank . chang, 2020/08/06
- [RFC v3 24/71] target/riscv: rvv-1.0: amo operations, frank . chang, 2020/08/06
- [RFC v3 25/71] target/riscv: rvv-1.0: load/store whole register instructions, frank . chang, 2020/08/06
- [RFC v3 26/71] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns, frank . chang, 2020/08/06
- Re: [RFC v3 26/71] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns, Frank Chang, 2020/08/15
[RFC v3 28/71] target/riscv: rvv-1.0: floating-point square-root instruction, frank . chang, 2020/08/06
[RFC v3 27/71] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation, frank . chang, 2020/08/06
[RFC v3 29/71] target/riscv: rvv-1.0: floating-point classify instructions, frank . chang, 2020/08/06
[RFC v3 32/71] target/riscv: rvv-1.0: set-X-first mask bit instructions, frank . chang, 2020/08/06
[RFC v3 30/71] target/riscv: rvv-1.0: mask population count instruction, frank . chang, 2020/08/06
[RFC v3 31/71] target/riscv: rvv-1.0: find-first-set mask bit instruction, frank . chang, 2020/08/06
[RFC v3 33/71] target/riscv: rvv-1.0: iota instruction, frank . chang, 2020/08/06
[RFC v3 34/71] target/riscv: rvv-1.0: element index instruction, frank . chang, 2020/08/06