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[RFC v3 28/71] target/riscv: rvv-1.0: floating-point square-root instruc
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From: |
frank . chang |
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Subject: |
[RFC v3 28/71] target/riscv: rvv-1.0: floating-point square-root instruction |
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Date: |
Thu, 6 Aug 2020 18:46:25 +0800 |
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/insn32.decode | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index c99575d1360..f142aa5d073 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -527,7 +527,7 @@ vfwmsac_vv 111110 . ..... ..... 001 ..... 1010111 @r_vm
vfwmsac_vf 111110 . ..... ..... 101 ..... 1010111 @r_vm
vfwnmsac_vv 111111 . ..... ..... 001 ..... 1010111 @r_vm
vfwnmsac_vf 111111 . ..... ..... 101 ..... 1010111 @r_vm
-vfsqrt_v 100011 . ..... 00000 001 ..... 1010111 @r2_vm
+vfsqrt_v 010011 . ..... 00000 001 ..... 1010111 @r2_vm
vfmin_vv 000100 . ..... ..... 001 ..... 1010111 @r_vm
vfmin_vf 000100 . ..... ..... 101 ..... 1010111 @r_vm
vfmax_vv 000110 . ..... ..... 001 ..... 1010111 @r_vm
--
2.17.1
- [RFC v3 24/71] target/riscv: rvv-1.0: amo operations, (continued)
- [RFC v3 24/71] target/riscv: rvv-1.0: amo operations, frank . chang, 2020/08/06
- [RFC v3 25/71] target/riscv: rvv-1.0: load/store whole register instructions, frank . chang, 2020/08/06
- [RFC v3 26/71] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns, frank . chang, 2020/08/06
- Re: [RFC v3 26/71] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns, Richard Henderson, 2020/08/06
- Re: [RFC v3 26/71] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns, Frank Chang, 2020/08/13
- Re: [RFC v3 26/71] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns, Richard Henderson, 2020/08/14
- Re: [RFC v3 26/71] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns, Frank Chang, 2020/08/15
- Re: [RFC v3 26/71] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns, Richard Henderson, 2020/08/15
- Re: [RFC v3 26/71] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns, Frank Chang, 2020/08/15
- Re: [RFC v3 26/71] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns, Frank Chang, 2020/08/15
[RFC v3 28/71] target/riscv: rvv-1.0: floating-point square-root instruction,
frank . chang <=
[RFC v3 27/71] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation, frank . chang, 2020/08/06
[RFC v3 29/71] target/riscv: rvv-1.0: floating-point classify instructions, frank . chang, 2020/08/06
[RFC v3 32/71] target/riscv: rvv-1.0: set-X-first mask bit instructions, frank . chang, 2020/08/06
[RFC v3 30/71] target/riscv: rvv-1.0: mask population count instruction, frank . chang, 2020/08/06
[RFC v3 31/71] target/riscv: rvv-1.0: find-first-set mask bit instruction, frank . chang, 2020/08/06
[RFC v3 33/71] target/riscv: rvv-1.0: iota instruction, frank . chang, 2020/08/06
[RFC v3 34/71] target/riscv: rvv-1.0: element index instruction, frank . chang, 2020/08/06
[RFC v3 35/71] target/riscv: rvv-1.0: allow load element with sign-extended, frank . chang, 2020/08/06
[RFC v3 36/71] target/riscv: rvv-1.0: register gather instructions, frank . chang, 2020/08/06
[RFC v3 38/71] target/riscv: rvv-1.0: floating-point move instruction, frank . chang, 2020/08/06