[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[RFC v4 41/70] target/riscv: rvv-1.0: single-width bit shift instruction
|
From: |
frank . chang |
|
Subject: |
[RFC v4 41/70] target/riscv: rvv-1.0: single-width bit shift instructions |
|
Date: |
Mon, 17 Aug 2020 16:49:26 +0800 |
From: Frank Chang <frank.chang@sifive.com>
Truncate vsll.vi, vsrl.vi, vsra.vi's immediate values to lg2(SEW) bits.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/insn_trans/trans_rvv.inc.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target/riscv/insn_trans/trans_rvv.inc.c
index 16e0941efb6..b763c3956cb 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -1915,9 +1915,9 @@ GEN_OPIVX_GVEC_SHIFT_TRANS(vsll_vx, shls)
GEN_OPIVX_GVEC_SHIFT_TRANS(vsrl_vx, shrs)
GEN_OPIVX_GVEC_SHIFT_TRANS(vsra_vx, sars)
-GEN_OPIVI_GVEC_TRANS(vsll_vi, IMM_ZX, vsll_vx, shli)
-GEN_OPIVI_GVEC_TRANS(vsrl_vi, IMM_ZX, vsrl_vx, shri)
-GEN_OPIVI_GVEC_TRANS(vsra_vi, IMM_ZX, vsra_vx, sari)
+GEN_OPIVI_GVEC_TRANS(vsll_vi, IMM_TRUNC_SEW, vsll_vx, shli)
+GEN_OPIVI_GVEC_TRANS(vsrl_vi, IMM_TRUNC_SEW, vsrl_vx, shri)
+GEN_OPIVI_GVEC_TRANS(vsra_vi, IMM_TRUNC_SEW, vsra_vx, sari)
/* Vector Narrowing Integer Right Shift Instructions */
static bool opivv_narrow_check(DisasContext *s, arg_rmrr *a)
--
2.17.1
- [RFC v4 37/70] target/riscv: rvv-1.0: floating-point scalar move instructions, (continued)
- [RFC v4 37/70] target/riscv: rvv-1.0: floating-point scalar move instructions, frank . chang, 2020/08/17
- [RFC v4 39/70] target/riscv: rvv-1.0: integer extension instructions, frank . chang, 2020/08/17
- [RFC v4 38/70] target/riscv: rvv-1.0: whole register move instructions, frank . chang, 2020/08/17
- [RFC v4 42/70] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow, frank . chang, 2020/08/17
- [RFC v4 43/70] target/riscv: rvv-1.0: narrowing integer right shift instructions, frank . chang, 2020/08/17
- [RFC v4 40/70] target/riscv: rvv-1.0: single-width averaging add and subtract instructions, frank . chang, 2020/08/17
- [RFC v4 41/70] target/riscv: rvv-1.0: single-width bit shift instructions,
frank . chang <=
- [RFC v4 44/70] target/riscv: rvv-1.0: widening integer multiply-add instructions, frank . chang, 2020/08/17
- [RFC v4 45/70] target/riscv: rvv-1.0: add Zvqmac extension, frank . chang, 2020/08/17
- [RFC v4 46/70] target/riscv: rvv-1.0: quad-widening integer multiply-add instructions, frank . chang, 2020/08/17
- [RFC v4 47/70] target/riscv: rvv-1.0: single-width saturating add and subtract instructions, frank . chang, 2020/08/17
- [RFC v4 48/70] target/riscv: rvv-1.0: integer comparison instructions, frank . chang, 2020/08/17