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[RFC v4 45/70] target/riscv: rvv-1.0: add Zvqmac extension
From: |
frank . chang |
Subject: |
[RFC v4 45/70] target/riscv: rvv-1.0: add Zvqmac extension |
Date: |
Mon, 17 Aug 2020 16:49:30 +0800 |
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/cpu.c | 1 +
target/riscv/cpu.h | 1 +
target/riscv/translate.c | 2 ++
3 files changed, 4 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 085381fee00..8844975bf94 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -512,6 +512,7 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
+ DEFINE_PROP_BOOL("Zvqmac", RISCVCPU, cfg.ext_vqmac, true),
DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 715faed8824..6e9b17c4e38 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -285,6 +285,7 @@ typedef struct RISCVCPU {
bool ext_counters;
bool ext_ifencei;
bool ext_icsr;
+ bool ext_vqmac;
char *priv_spec;
char *user_spec;
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 0b3f5f1b4ba..5817e9344e9 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -75,6 +75,7 @@ typedef struct DisasContext {
uint8_t sew;
uint16_t vlen;
bool vl_eq_vlmax;
+ bool ext_vqmac;
} DisasContext;
#ifdef TARGET_RISCV64
@@ -870,6 +871,7 @@ static void riscv_tr_init_disas_context(DisasContextBase
*dcbase, CPUState *cs)
ctx->misa = env->misa;
ctx->frm = -1; /* unknown rounding mode */
ctx->ext_ifencei = cpu->cfg.ext_ifencei;
+ ctx->ext_vqmac = cpu->cfg.ext_vqmac;
ctx->vlen = cpu->cfg.vlen;
ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL);
ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW);
--
2.17.1
- [RFC v4 39/70] target/riscv: rvv-1.0: integer extension instructions, (continued)
- [RFC v4 39/70] target/riscv: rvv-1.0: integer extension instructions, frank . chang, 2020/08/17
- [RFC v4 38/70] target/riscv: rvv-1.0: whole register move instructions, frank . chang, 2020/08/17
- [RFC v4 42/70] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow, frank . chang, 2020/08/17
- [RFC v4 43/70] target/riscv: rvv-1.0: narrowing integer right shift instructions, frank . chang, 2020/08/17
- [RFC v4 40/70] target/riscv: rvv-1.0: single-width averaging add and subtract instructions, frank . chang, 2020/08/17
- [RFC v4 41/70] target/riscv: rvv-1.0: single-width bit shift instructions, frank . chang, 2020/08/17
- [RFC v4 44/70] target/riscv: rvv-1.0: widening integer multiply-add instructions, frank . chang, 2020/08/17
- [RFC v4 45/70] target/riscv: rvv-1.0: add Zvqmac extension,
frank . chang <=
- [RFC v4 46/70] target/riscv: rvv-1.0: quad-widening integer multiply-add instructions, frank . chang, 2020/08/17
- [RFC v4 47/70] target/riscv: rvv-1.0: single-width saturating add and subtract instructions, frank . chang, 2020/08/17
- [RFC v4 48/70] target/riscv: rvv-1.0: integer comparison instructions, frank . chang, 2020/08/17
- [RFC v4 49/70] target/riscv: use softfloat lib float16 comparison functions, frank . chang, 2020/08/17
- [RFC v4 50/70] target/riscv: rvv-1.0: floating-point compare instructions, frank . chang, 2020/08/17