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[RFC v4 48/70] target/riscv: rvv-1.0: integer comparison instructions
From: |
frank . chang |
Subject: |
[RFC v4 48/70] target/riscv: rvv-1.0: integer comparison instructions |
Date: |
Mon, 17 Aug 2020 16:49:33 +0800 |
From: Frank Chang <frank.chang@sifive.com>
* Sign-extend vmselu.vi and vmsgtu.vi immediate values.
* Remove "set tail elements to zeros" as tail elements can be unchanged
for either VTA to have undisturbed or agnostic setting.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn_trans/trans_rvv.inc.c | 4 ++--
target/riscv/vector_helper.c | 8 --------
2 files changed, 2 insertions(+), 10 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target/riscv/insn_trans/trans_rvv.inc.c
index ef100254830..c3be3dd97ff 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2090,9 +2090,9 @@ GEN_OPIVX_TRANS(vmsgt_vx, opivx_cmp_check)
GEN_OPIVI_TRANS(vmseq_vi, IMM_SX, vmseq_vx, opivx_cmp_check)
GEN_OPIVI_TRANS(vmsne_vi, IMM_SX, vmsne_vx, opivx_cmp_check)
-GEN_OPIVI_TRANS(vmsleu_vi, IMM_ZX, vmsleu_vx, opivx_cmp_check)
+GEN_OPIVI_TRANS(vmsleu_vi, IMM_SX, vmsleu_vx, opivx_cmp_check)
GEN_OPIVI_TRANS(vmsle_vi, IMM_SX, vmsle_vx, opivx_cmp_check)
-GEN_OPIVI_TRANS(vmsgtu_vi, IMM_ZX, vmsgtu_vx, opivx_cmp_check)
+GEN_OPIVI_TRANS(vmsgtu_vi, IMM_SX, vmsgtu_vx, opivx_cmp_check)
GEN_OPIVI_TRANS(vmsgt_vi, IMM_SX, vmsgt_vx, opivx_cmp_check)
/* Vector Integer Min/Max Instructions */
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 544c8e38fca..f80c13b0857 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -1403,7 +1403,6 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void
*vs2, \
{ \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
- uint32_t vlmax = vext_maxsz(desc) / sizeof(ETYPE); \
uint32_t i; \
\
for (i = 0; i < vl; i++) { \
@@ -1414,9 +1413,6 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void
*vs2, \
} \
vext_set_elem_mask(vd, i, DO_OP(s2, s1)); \
} \
- for (; i < vlmax; i++) { \
- vext_set_elem_mask(vd, i, 0); \
- } \
}
GEN_VEXT_CMP_VV(vmseq_vv_b, uint8_t, H1, DO_MSEQ)
@@ -1455,7 +1451,6 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1,
void *vs2, \
{ \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
- uint32_t vlmax = vext_maxsz(desc) / sizeof(ETYPE); \
uint32_t i; \
\
for (i = 0; i < vl; i++) { \
@@ -1466,9 +1461,6 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1,
void *vs2, \
vext_set_elem_mask(vd, i, \
DO_OP(s2, (ETYPE)(target_long)s1)); \
} \
- for (; i < vlmax; i++) { \
- vext_set_elem_mask(vd, i, 0); \
- } \
}
GEN_VEXT_CMP_VX(vmseq_vx_b, uint8_t, H1, DO_MSEQ)
--
2.17.1
- Re: [RFC v4 40/70] target/riscv: rvv-1.0: single-width averaging add and subtract instructions, (continued)
- [RFC v4 41/70] target/riscv: rvv-1.0: single-width bit shift instructions, frank . chang, 2020/08/17
- [RFC v4 44/70] target/riscv: rvv-1.0: widening integer multiply-add instructions, frank . chang, 2020/08/17
- [RFC v4 45/70] target/riscv: rvv-1.0: add Zvqmac extension, frank . chang, 2020/08/17
- [RFC v4 46/70] target/riscv: rvv-1.0: quad-widening integer multiply-add instructions, frank . chang, 2020/08/17
- [RFC v4 47/70] target/riscv: rvv-1.0: single-width saturating add and subtract instructions, frank . chang, 2020/08/17
- [RFC v4 48/70] target/riscv: rvv-1.0: integer comparison instructions,
frank . chang <=
- [RFC v4 49/70] target/riscv: use softfloat lib float16 comparison functions, frank . chang, 2020/08/17
- [RFC v4 50/70] target/riscv: rvv-1.0: floating-point compare instructions, frank . chang, 2020/08/17
- [RFC v4 51/70] target/riscv: rvv-1.0: mask-register logical instructions, frank . chang, 2020/08/17
- [RFC v4 52/70] target/riscv: rvv-1.0: slide instructions, frank . chang, 2020/08/17
- [RFC v4 53/70] target/riscv: rvv-1.0: floating-point slide instructions, frank . chang, 2020/08/17