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[PULL 00/40] ppc-for-5.2 queue 20200818
From: |
David Gibson |
Subject: |
[PULL 00/40] ppc-for-5.2 queue 20200818 |
Date: |
Tue, 18 Aug 2020 14:18:42 +1000 |
The following changes since commit d0ed6a69d399ae193959225cdeaa9382746c91cc:
Update version for v5.1.0 release (2020-08-11 17:07:03 +0100)
are available in the Git repository at:
git://github.com/dgibson/qemu.git tags/ppc-for-5.2-20200818
for you to fetch changes up to 3110f0ee19ccdb50adff3dfa1321039f69efddcd:
spapr/xive: Use xive_source_esb_len() (2020-08-14 13:35:45 +1000)
----------------------------------------------------------------
ppc patch queue 2020-08-18
Here's my first pull request for qemu-5.2, which has quite a few
accumulated things. Highlights are:
* Preliminary support for POWER10 (Power ISA 3.1) instruction emulation
* Add documentation on the (very confusing) pseries NUMA configuration
* Fix some bugs handling edge cases with XICS, XIVE and kernel_irqchip
* Fix icount for a number of POWER registers
* Many cleanups to error handling in XIVE code
* Validate size of -prom-env data
----------------------------------------------------------------
Anton Blanchard (1):
ppc/spapr: Fix 32 bit logical memory block size assumptions
Cédric Le Goater (1):
docs: Update POWER9 XIVE support for nested guests
Daniel Henrique Barboza (1):
docs: adding NUMA documentation for pseries
Greg Kurz (24):
spapr: Use error_append_hint() in spapr_caps.c
spapr: Forbid nested KVM-HV in pre-power9 compat mode
spapr: Clarify error and documentation for broken KVM XICS
spapr/xive: Fix xive->fd if kvm_create_device() fails
spapr/xive: Simplify kvmppc_xive_disconnect()
ppc/xive: Rework setup of XiveSource::esb_mmio
ppc/xive: Introduce dedicated kvm_irqchip_in_kernel() wrappers
spapr/xive: Convert KVM device fd checks to assert()
spapr: Simplify error handling in spapr_phb_realize()
spapr/xive: Rework error handling of kvmppc_xive_cpu_connect()
spapr/xive: Rework error handling of kvmppc_xive_source_reset()
spapr/xive: Rework error handling of kvmppc_xive_mmap()
spapr/xive: Rework error handling of kvmppc_xive_cpu_[gs]et_state()
spapr/xive: Rework error handling of kvmppc_xive_[gs]et_queue_config()
spapr/xive: Rework error handling in kvmppc_xive_get_queues()
spapr/xive: Rework error handling of kvmppc_xive_set_source_config()
spapr/kvm: Fix error handling in kvmppc_xive_pre_save()
spapr/xive: Fix error handling in kvmppc_xive_post_load()
ppc/xive: Fix error handling in vmstate_xive_tctx_*() callbacks
spapr/xive: Simplify error handling in kvmppc_xive_connect()
ppc/xive: Simplify error handling in xive_tctx_realize()
spapr/xive: Simplify error handling of kvmppc_xive_cpu_synchronize_state()
nvram: Exit QEMU if NVRAM cannot contain all -prom-env data
spapr/xive: Use xive_source_esb_len()
Gustavo Romero (2):
ppc/xive: Fix some typos in comments
target/ppc: Integrate icount to purr, vtb, and tbu40
Lijun Pan (9):
target/ppc: Introduce Power ISA 3.1 flag
target/ppc: Enable Power ISA 3.1
target/ppc: add byte-reverse br[dwh] instructions
target/ppc: convert vmuluwm to tcg_gen_gvec_mul
target/ppc: add vmulld instruction
Update PowerPC AT_HWCAP2 definition
target/ppc: add vmulld to INDEX_op_mul_vec case
target/ppc: add vmulh{su}w instructions
target/ppc: add vmulh{su}d instructions
Matthieu Bucchianeri (2):
target/ppc: Fix TCG leak with the evmwsmiaa instruction
target/ppc: Fix SPE unavailable exception triggering
docs/specs/index.rst | 1 +
docs/specs/ppc-spapr-numa.rst | 191 +++++++++++++++++++++++++++
docs/specs/ppc-spapr-xive.rst | 10 +-
hw/intc/spapr_xive.c | 47 ++++---
hw/intc/spapr_xive_kvm.c | 257 +++++++++++++++++-------------------
hw/intc/xive.c | 57 +++++---
hw/nvram/chrp_nvram.c | 24 +++-
hw/nvram/mac_nvram.c | 2 +-
hw/nvram/spapr_nvram.c | 3 +-
hw/ppc/spapr.c | 6 +-
hw/ppc/spapr_caps.c | 99 ++++++++------
hw/ppc/spapr_irq.c | 12 +-
hw/ppc/spapr_pci.c | 16 +--
hw/sparc/sun4m.c | 2 +-
hw/sparc64/sun4u.c | 2 +-
include/elf.h | 1 +
include/hw/nvram/chrp_nvram.h | 3 +-
include/hw/ppc/spapr_xive.h | 8 +-
include/hw/ppc/xive.h | 15 ++-
target/ppc/cpu.h | 4 +-
target/ppc/helper.h | 5 +-
target/ppc/int_helper.c | 48 +++++--
target/ppc/translate.c | 40 ++++++
target/ppc/translate/spe-impl.inc.c | 101 +++++++++-----
target/ppc/translate/vmx-impl.inc.c | 11 +-
target/ppc/translate/vmx-ops.inc.c | 10 +-
target/ppc/translate_init.inc.c | 32 ++++-
tcg/ppc/tcg-target.h | 2 +
tcg/ppc/tcg-target.inc.c | 12 +-
29 files changed, 719 insertions(+), 302 deletions(-)
create mode 100644 docs/specs/ppc-spapr-numa.rst
- [PULL 00/40] ppc-for-5.2 queue 20200818,
David Gibson <=
- [PULL 01/40] target/ppc: Fix TCG leak with the evmwsmiaa instruction, David Gibson, 2020/08/18
- [PULL 02/40] target/ppc: Introduce Power ISA 3.1 flag, David Gibson, 2020/08/18
- [PULL 04/40] target/ppc: add byte-reverse br[dwh] instructions, David Gibson, 2020/08/18
- [PULL 03/40] target/ppc: Enable Power ISA 3.1, David Gibson, 2020/08/18
- [PULL 06/40] target/ppc: add vmulld instruction, David Gibson, 2020/08/18
- [PULL 08/40] spapr: Use error_append_hint() in spapr_caps.c, David Gibson, 2020/08/18
- [PULL 09/40] spapr: Forbid nested KVM-HV in pre-power9 compat mode, David Gibson, 2020/08/18
- [PULL 07/40] ppc/spapr: Fix 32 bit logical memory block size assumptions, David Gibson, 2020/08/18
- [PULL 05/40] target/ppc: convert vmuluwm to tcg_gen_gvec_mul, David Gibson, 2020/08/18
- [PULL 12/40] target/ppc: add vmulld to INDEX_op_mul_vec case, David Gibson, 2020/08/18