[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 04/40] target/ppc: add byte-reverse br[dwh] instructions
From: |
David Gibson |
Subject: |
[PULL 04/40] target/ppc: add byte-reverse br[dwh] instructions |
Date: |
Tue, 18 Aug 2020 14:18:46 +1000 |
From: Lijun Pan <ljp@linux.ibm.com>
POWER ISA 3.1 introduces following byte-reverse instructions:
brd: Byte-Reverse Doubleword X-form
brw: Byte-Reverse Word X-form
brh: Byte-Reverse Halfword X-form
Signed-off-by: Lijun Pan <ljp@linux.ibm.com>
Message-Id: <20200701234344.91843-4-ljp@linux.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/translate.c | 40 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 40 insertions(+)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 4ce3d664b5..590c3e3bc7 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -6971,7 +6971,47 @@ static void gen_dform3D(DisasContext *ctx)
return gen_invalid(ctx);
}
+#if defined(TARGET_PPC64)
+/* brd */
+static void gen_brd(DisasContext *ctx)
+{
+ tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
+}
+
+/* brw */
+static void gen_brw(DisasContext *ctx)
+{
+ tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
+ tcg_gen_rotli_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 32);
+
+}
+
+/* brh */
+static void gen_brh(DisasContext *ctx)
+{
+ TCGv_i64 t0 = tcg_temp_new_i64();
+ TCGv_i64 t1 = tcg_temp_new_i64();
+ TCGv_i64 t2 = tcg_temp_new_i64();
+
+ tcg_gen_movi_i64(t0, 0x00ff00ff00ff00ffull);
+ tcg_gen_shri_i64(t1, cpu_gpr[rS(ctx->opcode)], 8);
+ tcg_gen_and_i64(t2, t1, t0);
+ tcg_gen_and_i64(t1, cpu_gpr[rS(ctx->opcode)], t0);
+ tcg_gen_shli_i64(t1, t1, 8);
+ tcg_gen_or_i64(cpu_gpr[rA(ctx->opcode)], t1, t2);
+
+ tcg_temp_free_i64(t0);
+ tcg_temp_free_i64(t1);
+ tcg_temp_free_i64(t2);
+}
+#endif
+
static opcode_t opcodes[] = {
+#if defined(TARGET_PPC64)
+GEN_HANDLER_E(brd, 0x1F, 0x1B, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA310),
+GEN_HANDLER_E(brw, 0x1F, 0x1B, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA310),
+GEN_HANDLER_E(brh, 0x1F, 0x1B, 0x06, 0x0000F801, PPC_NONE, PPC2_ISA310),
+#endif
GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
--
2.26.2
- [PULL 00/40] ppc-for-5.2 queue 20200818, David Gibson, 2020/08/18
- [PULL 01/40] target/ppc: Fix TCG leak with the evmwsmiaa instruction, David Gibson, 2020/08/18
- [PULL 02/40] target/ppc: Introduce Power ISA 3.1 flag, David Gibson, 2020/08/18
- [PULL 04/40] target/ppc: add byte-reverse br[dwh] instructions,
David Gibson <=
- [PULL 03/40] target/ppc: Enable Power ISA 3.1, David Gibson, 2020/08/18
- [PULL 06/40] target/ppc: add vmulld instruction, David Gibson, 2020/08/18
- [PULL 08/40] spapr: Use error_append_hint() in spapr_caps.c, David Gibson, 2020/08/18
- [PULL 09/40] spapr: Forbid nested KVM-HV in pre-power9 compat mode, David Gibson, 2020/08/18
- [PULL 07/40] ppc/spapr: Fix 32 bit logical memory block size assumptions, David Gibson, 2020/08/18
- [PULL 05/40] target/ppc: convert vmuluwm to tcg_gen_gvec_mul, David Gibson, 2020/08/18
- [PULL 12/40] target/ppc: add vmulld to INDEX_op_mul_vec case, David Gibson, 2020/08/18
- [PULL 11/40] Update PowerPC AT_HWCAP2 definition, David Gibson, 2020/08/18
- [PULL 14/40] target/ppc: add vmulh{su}d instructions, David Gibson, 2020/08/18
- [PULL 16/40] docs: adding NUMA documentation for pseries, David Gibson, 2020/08/18