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[PULL 02/40] target/ppc: Introduce Power ISA 3.1 flag
From: |
David Gibson |
Subject: |
[PULL 02/40] target/ppc: Introduce Power ISA 3.1 flag |
Date: |
Tue, 18 Aug 2020 14:18:44 +1000 |
From: Lijun Pan <ljp@linux.ibm.com>
This flag will be used for Power10 instructions.
Signed-off-by: Lijun Pan <ljp@linux.ibm.com>
Message-Id: <20200701234344.91843-2-ljp@linux.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/cpu.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index e7d382ac10..7bfee8211f 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -2191,6 +2191,8 @@ enum {
PPC2_PM_ISA206 = 0x0000000000040000ULL,
/* POWER ISA 3.0 */
PPC2_ISA300 = 0x0000000000080000ULL,
+ /* POWER ISA 3.1 */
+ PPC2_ISA310 = 0x0000000000100000ULL,
#define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \
PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206 | \
--
2.26.2
- [PULL 00/40] ppc-for-5.2 queue 20200818, David Gibson, 2020/08/18
- [PULL 01/40] target/ppc: Fix TCG leak with the evmwsmiaa instruction, David Gibson, 2020/08/18
- [PULL 02/40] target/ppc: Introduce Power ISA 3.1 flag,
David Gibson <=
- [PULL 04/40] target/ppc: add byte-reverse br[dwh] instructions, David Gibson, 2020/08/18
- [PULL 03/40] target/ppc: Enable Power ISA 3.1, David Gibson, 2020/08/18
- [PULL 06/40] target/ppc: add vmulld instruction, David Gibson, 2020/08/18
- [PULL 08/40] spapr: Use error_append_hint() in spapr_caps.c, David Gibson, 2020/08/18
- [PULL 09/40] spapr: Forbid nested KVM-HV in pre-power9 compat mode, David Gibson, 2020/08/18
- [PULL 07/40] ppc/spapr: Fix 32 bit logical memory block size assumptions, David Gibson, 2020/08/18
- [PULL 05/40] target/ppc: convert vmuluwm to tcg_gen_gvec_mul, David Gibson, 2020/08/18
- [PULL 12/40] target/ppc: add vmulld to INDEX_op_mul_vec case, David Gibson, 2020/08/18
- [PULL 11/40] Update PowerPC AT_HWCAP2 definition, David Gibson, 2020/08/18
- [PULL 14/40] target/ppc: add vmulh{su}d instructions, David Gibson, 2020/08/18