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[PULL v2 30/69] target/mips: Replace gen_exception_err(err=0) by gen_exc
From: |
Philippe Mathieu-Daudé |
Subject: |
[PULL v2 30/69] target/mips: Replace gen_exception_err(err=0) by gen_exception_end() |
Date: |
Thu, 14 Jan 2021 17:20:01 +0100 |
generate_exception_err(err=0) is simply generate_exception_end().
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201214183739.500368-11-f4bug@amsat.org>
---
target/mips/translate.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 72cbf604ac3..fa11c8ffe0c 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -2897,7 +2897,7 @@ void gen_move_high32(TCGv ret, TCGv_i64 arg)
static inline void check_cp0_enabled(DisasContext *ctx)
{
if (unlikely(!(ctx->hflags & MIPS_HFLAG_CP0))) {
- generate_exception_err(ctx, EXCP_CpU, 0);
+ generate_exception_end(ctx, EXCP_CpU);
}
}
@@ -3103,10 +3103,10 @@ static inline void check_mt(DisasContext *ctx)
static inline void check_cp0_mt(DisasContext *ctx)
{
if (unlikely(!(ctx->hflags & MIPS_HFLAG_CP0))) {
- generate_exception_err(ctx, EXCP_CpU, 0);
+ generate_exception_end(ctx, EXCP_CpU);
} else {
if (unlikely(!(ctx->CP0_Config3 & (1 << CP0C3_MT)))) {
- generate_exception_err(ctx, EXCP_RI, 0);
+ generate_exception_end(ctx, EXCP_RI);
}
}
}
--
2.26.2
- [PULL v2 00/69] MIPS patches for 2021-01-14, Philippe Mathieu-Daudé, 2021/01/14
- [PULL v2 29/69] target/mips/translate: Add declarations for generic code, Philippe Mathieu-Daudé, 2021/01/14
- [PULL v2 30/69] target/mips: Replace gen_exception_err(err=0) by gen_exception_end(),
Philippe Mathieu-Daudé <=
- [PULL v2 31/69] target/mips: Replace gen_exception_end(EXCP_RI) by gen_rsvd_instruction, Philippe Mathieu-Daudé, 2021/01/14
- [PULL v2 32/69] target/mips: Declare generic FPU / Coprocessor functions in translate.h, Philippe Mathieu-Daudé, 2021/01/14
- [PULL v2 36/69] target/mips/translate: Expose check_mips_64() to 32-bit mode, Philippe Mathieu-Daudé, 2021/01/14
- [PULL v2 35/69] target/mips/translate: Extract decode_opc_legacy() from decode_opc(), Philippe Mathieu-Daudé, 2021/01/14
- [PULL v2 52/69] target/mips: Introduce decode tree bindings for MSA ASE, Philippe Mathieu-Daudé, 2021/01/14
- [PULL v2 53/69] target/mips: Use decode_ase_msa() generated from decodetree, Philippe Mathieu-Daudé, 2021/01/14
- [PULL v2 54/69] target/mips: Extract LSA/DLSA translation generators, Philippe Mathieu-Daudé, 2021/01/14
- [PULL v2 55/69] target/mips: Introduce decodetree helpers for MSA LSA/DLSA opcodes, Philippe Mathieu-Daudé, 2021/01/14
- [PULL v2 58/69] target/mips: Convert Rel6 Special2 opcode to decodetree, Philippe Mathieu-Daudé, 2021/01/14
- [PULL v2 56/69] target/mips: Introduce decodetree helpers for Release6 LSA/DLSA opcodes, Philippe Mathieu-Daudé, 2021/01/14