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[PULL v2 36/69] target/mips/translate: Expose check_mips_64() to 32-bit
From: |
Philippe Mathieu-Daudé |
Subject: |
[PULL v2 36/69] target/mips/translate: Expose check_mips_64() to 32-bit mode |
Date: |
Thu, 14 Jan 2021 17:20:05 +0100 |
To allow compiling 64-bit specific translation code more
generically (and removing #ifdef'ry), allow compiling
check_mips_64() on 32-bit targets.
If ever called on 32-bit, we obviously emit a reserved
instruction exception.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20201215225757.764263-3-f4bug@amsat.org>
---
target/mips/translate.h | 2 --
target/mips/translate.c | 8 +++-----
2 files changed, 3 insertions(+), 7 deletions(-)
diff --git a/target/mips/translate.h b/target/mips/translate.h
index 1b918a439b1..60e59675ef1 100644
--- a/target/mips/translate.h
+++ b/target/mips/translate.h
@@ -129,9 +129,7 @@ void generate_exception_end(DisasContext *ctx, int excp);
void gen_reserved_instruction(DisasContext *ctx);
void check_insn(DisasContext *ctx, uint64_t flags);
-#ifdef TARGET_MIPS64
void check_mips_64(DisasContext *ctx);
-#endif
void check_cp0_enabled(DisasContext *ctx);
void check_cp1_enabled(DisasContext *ctx);
void check_cp1_64bitmode(DisasContext *ctx);
diff --git a/target/mips/translate.c b/target/mips/translate.c
index d4d5d294f34..7e8afb363ac 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -2971,18 +2971,16 @@ static inline void check_ps(DisasContext *ctx)
check_cp1_64bitmode(ctx);
}
-#ifdef TARGET_MIPS64
/*
- * This code generates a "reserved instruction" exception if 64-bit
- * instructions are not enabled.
+ * This code generates a "reserved instruction" exception if cpu is not
+ * 64-bit or 64-bit instructions are not enabled.
*/
void check_mips_64(DisasContext *ctx)
{
- if (unlikely(!(ctx->hflags & MIPS_HFLAG_64))) {
+ if (unlikely((TARGET_LONG_BITS != 64) || !(ctx->hflags & MIPS_HFLAG_64))) {
gen_reserved_instruction(ctx);
}
}
-#endif
#ifndef CONFIG_USER_ONLY
static inline void check_mvh(DisasContext *ctx)
--
2.26.2
- [PULL v2 00/69] MIPS patches for 2021-01-14, Philippe Mathieu-Daudé, 2021/01/14
- [PULL v2 29/69] target/mips/translate: Add declarations for generic code, Philippe Mathieu-Daudé, 2021/01/14
- [PULL v2 30/69] target/mips: Replace gen_exception_err(err=0) by gen_exception_end(), Philippe Mathieu-Daudé, 2021/01/14
- [PULL v2 31/69] target/mips: Replace gen_exception_end(EXCP_RI) by gen_rsvd_instruction, Philippe Mathieu-Daudé, 2021/01/14
- [PULL v2 32/69] target/mips: Declare generic FPU / Coprocessor functions in translate.h, Philippe Mathieu-Daudé, 2021/01/14
- [PULL v2 36/69] target/mips/translate: Expose check_mips_64() to 32-bit mode,
Philippe Mathieu-Daudé <=
- [PULL v2 35/69] target/mips/translate: Extract decode_opc_legacy() from decode_opc(), Philippe Mathieu-Daudé, 2021/01/14
- [PULL v2 52/69] target/mips: Introduce decode tree bindings for MSA ASE, Philippe Mathieu-Daudé, 2021/01/14
- [PULL v2 53/69] target/mips: Use decode_ase_msa() generated from decodetree, Philippe Mathieu-Daudé, 2021/01/14
- [PULL v2 54/69] target/mips: Extract LSA/DLSA translation generators, Philippe Mathieu-Daudé, 2021/01/14
- [PULL v2 55/69] target/mips: Introduce decodetree helpers for MSA LSA/DLSA opcodes, Philippe Mathieu-Daudé, 2021/01/14
- [PULL v2 58/69] target/mips: Convert Rel6 Special2 opcode to decodetree, Philippe Mathieu-Daudé, 2021/01/14
- [PULL v2 56/69] target/mips: Introduce decodetree helpers for Release6 LSA/DLSA opcodes, Philippe Mathieu-Daudé, 2021/01/14
- [PULL v2 57/69] target/mips: Remove now unreachable LSA/DLSA opcodes code, Philippe Mathieu-Daudé, 2021/01/14
- [PULL v2 63/69] target/mips: Convert Rel6 LDL/LDR/SDL/SDR opcodes to decodetree, Philippe Mathieu-Daudé, 2021/01/14
- [PULL v2 66/69] target/mips: Remove CPU_R5900 definition, Philippe Mathieu-Daudé, 2021/01/14