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[PULL v2 55/69] target/mips: Introduce decodetree helpers for MSA LSA/DL
From: |
Philippe Mathieu-Daudé |
Subject: |
[PULL v2 55/69] target/mips: Introduce decodetree helpers for MSA LSA/DLSA opcodes |
Date: |
Thu, 14 Jan 2021 17:20:09 +0100 |
Add the LSA opcode to the MSA32 decodetree config, add DLSA
to a new config for the MSA64 ASE, and call decode_msa64()
in the main decode_opc() loop.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201215225757.764263-23-f4bug@amsat.org>
---
target/mips/msa32.decode | 5 +++++
target/mips/msa64.decode | 17 +++++++++++++++++
target/mips/msa_translate.c | 14 ++++++++++++++
target/mips/meson.build | 1 +
4 files changed, 37 insertions(+)
create mode 100644 target/mips/msa64.decode
diff --git a/target/mips/msa32.decode b/target/mips/msa32.decode
index d69675132b8..ca200e373b1 100644
--- a/target/mips/msa32.decode
+++ b/target/mips/msa32.decode
@@ -10,11 +10,16 @@
# (Document Number: MD00866-2B-MSA32-AFP-01.12)
#
+&rtype rs rt rd sa
+
&msa_bz df wt s16
+@lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &rtype
@bz ...... ... .. wt:5 s16:16 &msa_bz df=3
@bz_df ...... ... df:2 wt:5 s16:16 &msa_bz
+LSA 000000 ..... ..... ..... 000 .. 000101 @lsa
+
BZ_V 010001 01011 ..... ................ @bz
BNZ_V 010001 01111 ..... ................ @bz
diff --git a/target/mips/msa64.decode b/target/mips/msa64.decode
new file mode 100644
index 00000000000..d2442474d0b
--- /dev/null
+++ b/target/mips/msa64.decode
@@ -0,0 +1,17 @@
+# MIPS SIMD Architecture Module instruction set
+#
+# Copyright (C) 2020 Philippe Mathieu-Daudé
+#
+# SPDX-License-Identifier: LGPL-2.1-or-later
+#
+# Reference:
+# MIPS Architecture for Programmers Volume IV-j
+# The MIPS64 SIMD Architecture Module, Revision 1.12
+# (Document Number: MD00868-1D-MSA64-AFP-01.12)
+#
+
+&rtype rs rt rd sa !extern
+
+@lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &rtype
+
+DLSA 000000 ..... ..... ..... 000 .. 010101 @lsa
diff --git a/target/mips/msa_translate.c b/target/mips/msa_translate.c
index 8a48f889aa2..ae6587edf69 100644
--- a/target/mips/msa_translate.c
+++ b/target/mips/msa_translate.c
@@ -19,6 +19,7 @@
/* Include the auto-generated decoder. */
#include "decode-msa32.c.inc"
+#include "decode-msa64.c.inc"
#define OPC_MSA (0x1E << 26)
@@ -2266,7 +2267,20 @@ static bool trans_MSA(DisasContext *ctx, arg_MSA *a)
return true;
}
+static bool trans_LSA(DisasContext *ctx, arg_rtype *a)
+{
+ return gen_lsa(ctx, a->rd, a->rt, a->rs, a->sa);
+}
+
+static bool trans_DLSA(DisasContext *ctx, arg_rtype *a)
+{
+ return gen_dlsa(ctx, a->rd, a->rt, a->rs, a->sa);
+}
+
bool decode_ase_msa(DisasContext *ctx, uint32_t insn)
{
+ if (TARGET_LONG_BITS == 64 && decode_msa64(ctx, insn)) {
+ return true;
+ }
return decode_msa32(ctx, insn);
}
diff --git a/target/mips/meson.build b/target/mips/meson.build
index 3810554343c..b63d8f150f1 100644
--- a/target/mips/meson.build
+++ b/target/mips/meson.build
@@ -1,5 +1,6 @@
gen = [
decodetree.process('msa32.decode', extra_args:
'--static-decode=decode_msa32'),
+ decodetree.process('msa64.decode', extra_args:
'--static-decode=decode_msa64'),
]
mips_ss = ss.source_set()
--
2.26.2
- [PULL v2 00/69] MIPS patches for 2021-01-14, Philippe Mathieu-Daudé, 2021/01/14
- [PULL v2 29/69] target/mips/translate: Add declarations for generic code, Philippe Mathieu-Daudé, 2021/01/14
- [PULL v2 30/69] target/mips: Replace gen_exception_err(err=0) by gen_exception_end(), Philippe Mathieu-Daudé, 2021/01/14
- [PULL v2 31/69] target/mips: Replace gen_exception_end(EXCP_RI) by gen_rsvd_instruction, Philippe Mathieu-Daudé, 2021/01/14
- [PULL v2 32/69] target/mips: Declare generic FPU / Coprocessor functions in translate.h, Philippe Mathieu-Daudé, 2021/01/14
- [PULL v2 36/69] target/mips/translate: Expose check_mips_64() to 32-bit mode, Philippe Mathieu-Daudé, 2021/01/14
- [PULL v2 35/69] target/mips/translate: Extract decode_opc_legacy() from decode_opc(), Philippe Mathieu-Daudé, 2021/01/14
- [PULL v2 52/69] target/mips: Introduce decode tree bindings for MSA ASE, Philippe Mathieu-Daudé, 2021/01/14
- [PULL v2 53/69] target/mips: Use decode_ase_msa() generated from decodetree, Philippe Mathieu-Daudé, 2021/01/14
- [PULL v2 54/69] target/mips: Extract LSA/DLSA translation generators, Philippe Mathieu-Daudé, 2021/01/14
- [PULL v2 55/69] target/mips: Introduce decodetree helpers for MSA LSA/DLSA opcodes,
Philippe Mathieu-Daudé <=
- [PULL v2 58/69] target/mips: Convert Rel6 Special2 opcode to decodetree, Philippe Mathieu-Daudé, 2021/01/14
- [PULL v2 56/69] target/mips: Introduce decodetree helpers for Release6 LSA/DLSA opcodes, Philippe Mathieu-Daudé, 2021/01/14
- [PULL v2 57/69] target/mips: Remove now unreachable LSA/DLSA opcodes code, Philippe Mathieu-Daudé, 2021/01/14
- [PULL v2 63/69] target/mips: Convert Rel6 LDL/LDR/SDL/SDR opcodes to decodetree, Philippe Mathieu-Daudé, 2021/01/14
- [PULL v2 66/69] target/mips: Remove CPU_R5900 definition, Philippe Mathieu-Daudé, 2021/01/14
- [PULL v2 67/69] target/mips: Remove CPU_NANOMIPS32 definition, Philippe Mathieu-Daudé, 2021/01/14
- [PULL v2 68/69] target/mips: Remove vendor specific CPU definitions, Philippe Mathieu-Daudé, 2021/01/14
- Re: [PULL v2 00/69] MIPS patches for 2021-01-14, Peter Maydell, 2021/01/15