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[PULL 37/54] hw/acpi/cxl: Pass in the CXLState directly rather than Mach
From: |
Michael S. Tsirkin |
Subject: |
[PULL 37/54] hw/acpi/cxl: Pass in the CXLState directly rather than MachineState |
Date: |
Fri, 10 Jun 2022 03:58:51 -0400 |
From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Refactoring step on path to moving all CXL state out of
MachineState.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Message-Id: <20220608145440.26106-3-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
include/hw/acpi/cxl.h | 5 +++--
hw/acpi/cxl.c | 9 ++++-----
hw/i386/acpi-build.c | 4 ++--
3 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/include/hw/acpi/cxl.h b/include/hw/acpi/cxl.h
index 0c496538c0..acf4418886 100644
--- a/include/hw/acpi/cxl.h
+++ b/include/hw/acpi/cxl.h
@@ -19,10 +19,11 @@
#define HW_ACPI_CXL_H
#include "hw/acpi/bios-linker-loader.h"
+#include "hw/cxl/cxl.h"
-void cxl_build_cedt(MachineState *ms, GArray *table_offsets, GArray
*table_data,
+void cxl_build_cedt(GArray *table_offsets, GArray *table_data,
BIOSLinker *linker, const char *oem_id,
- const char *oem_table_id);
+ const char *oem_table_id, CXLState *cxl_state);
void build_cxl_osc_method(Aml *dev);
#endif
diff --git a/hw/acpi/cxl.c b/hw/acpi/cxl.c
index 31d5235136..2bf8c07993 100644
--- a/hw/acpi/cxl.c
+++ b/hw/acpi/cxl.c
@@ -65,9 +65,8 @@ static void cedt_build_chbs(GArray *table_data, PXBDev *cxl)
* Interleave ways encoding in CXL 2.0 ECN: 3, 6, 12 and 16-way memory
* interleaving.
*/
-static void cedt_build_cfmws(GArray *table_data, MachineState *ms)
+static void cedt_build_cfmws(GArray *table_data, CXLState *cxls)
{
- CXLState *cxls = ms->cxl_devices_state;
GList *it;
for (it = cxls->fixed_windows; it; it = it->next) {
@@ -129,9 +128,9 @@ static int cxl_foreach_pxb_hb(Object *obj, void *opaque)
return 0;
}
-void cxl_build_cedt(MachineState *ms, GArray *table_offsets, GArray
*table_data,
+void cxl_build_cedt(GArray *table_offsets, GArray *table_data,
BIOSLinker *linker, const char *oem_id,
- const char *oem_table_id)
+ const char *oem_table_id, CXLState *cxl_state)
{
Aml *cedt;
AcpiTable table = { .sig = "CEDT", .rev = 1, .oem_id = oem_id,
@@ -144,7 +143,7 @@ void cxl_build_cedt(MachineState *ms, GArray
*table_offsets, GArray *table_data,
/* reserve space for CEDT header */
object_child_foreach_recursive(object_get_root(), cxl_foreach_pxb_hb,
cedt);
- cedt_build_cfmws(cedt->buf, ms);
+ cedt_build_cfmws(cedt->buf, cxl_state);
/* copy AML table into ACPI tables blob and patch header there */
g_array_append_vals(table_data, cedt->buf->data, cedt->buf->len);
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index f41e14a469..663c34b9d1 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -2615,8 +2615,8 @@ void acpi_build(AcpiBuildTables *tables, MachineState
*machine)
x86ms->oem_id, x86ms->oem_table_id);
}
if (machine->cxl_devices_state->is_enabled) {
- cxl_build_cedt(machine, table_offsets, tables_blob, tables->linker,
- x86ms->oem_id, x86ms->oem_table_id);
+ cxl_build_cedt(table_offsets, tables_blob, tables->linker,
+ x86ms->oem_id, x86ms->oem_table_id,
machine->cxl_devices_state);
}
acpi_add_table(table_offsets, tables_blob);
--
MST
- [PULL 27/54] tests: acpi: add pvpanic-isa: testcase, (continued)
- [PULL 27/54] tests: acpi: add pvpanic-isa: testcase, Michael S. Tsirkin, 2022/06/10
- [PULL 28/54] acpi: pvpanic-isa: use AcpiDevAmlIfClass:build_dev_aml to provide device's AML, Michael S. Tsirkin, 2022/06/10
- [PULL 29/54] tests: acpi: update expected DSDT.pvpanic-isa blob, Michael S. Tsirkin, 2022/06/10
- [PULL 30/54] tests: acpi: white-list DSDT.tis.tpm2/DSDT.tis.tpm12 expected blobs, Michael S. Tsirkin, 2022/06/10
- [PULL 34/54] tests: acpi: update expected DSDT.tis.tpm2/DSDT.tis.tpm12 blobs, Michael S. Tsirkin, 2022/06/10
- [PULL 32/54] acpi: pc/q35: remove not needed 'if' condition on pci bus, Michael S. Tsirkin, 2022/06/10
- [PULL 31/54] acpi: pc/q35: tpm-tis: fix TPM device scope, Michael S. Tsirkin, 2022/06/10
- [PULL 33/54] acpi: tpm-tis: use AcpiDevAmlIfClass:build_dev_aml to provide device's AML, Michael S. Tsirkin, 2022/06/10
- [PULL 38/54] hw/cxl: Push linking of CXL targets into i386/pc rather than in machine.c, Michael S. Tsirkin, 2022/06/10
- [PULL 39/54] tests/acpi: Allow modification of q35 CXL CEDT table., Michael S. Tsirkin, 2022/06/10
- [PULL 37/54] hw/acpi/cxl: Pass in the CXLState directly rather than MachineState,
Michael S. Tsirkin <=
- [PULL 40/54] pci/pci_expander_bridge: For CXL HB delay the HB register memory region setup., Michael S. Tsirkin, 2022/06/10
- [PULL 35/54] x86: acpi-build: do not include hw/isa/isa.h directly, Michael S. Tsirkin, 2022/06/10
- [PULL 43/54] hw/machine: Drop cxl_supported flag as no longer useful, Michael S. Tsirkin, 2022/06/10
- [PULL 42/54] hw/cxl: Move the CXLState from MachineState to machine type specific state., Michael S. Tsirkin, 2022/06/10
- [PULL 36/54] hw/cxl: Make the CXL fixed memory window setup a machine parameter., Michael S. Tsirkin, 2022/06/10
- [PULL 41/54] tests/acpi: Update q35/CEDT.cxl for new memory addresses., Michael S. Tsirkin, 2022/06/10
- [PULL 44/54] pci: fix overflow in snprintf string formatting, Michael S. Tsirkin, 2022/06/10
- [PULL 45/54] hw/cxl: Fix missing write mask for HDM decoder target list registers, Michael S. Tsirkin, 2022/06/10
- [PULL 46/54] hw/acpi/viot: rename build_pci_range_node() to enumerate_pci_host_bridges(), Michael S. Tsirkin, 2022/06/10
- [PULL 47/54] hw/acpi/viot: move the individual PCI host bridge entry generation to a new function, Michael S. Tsirkin, 2022/06/10