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[PULL 47/54] hw/acpi/viot: move the individual PCI host bridge entry gen
From: |
Michael S. Tsirkin |
Subject: |
[PULL 47/54] hw/acpi/viot: move the individual PCI host bridge entry generation to a new function |
Date: |
Fri, 10 Jun 2022 03:59:22 -0400 |
From: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Instead of generating each table entry inline, move the individual PCI host
bridge
table entry generation to a separate build_pci_host_range() function.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Ani Sinha <ani@anisinha.ca>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220525173232.31429-3-mark.cave-ayland@ilande.co.uk>
Reviewed-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/acpi/viot.c | 48 +++++++++++++++++++++++++++---------------------
1 file changed, 27 insertions(+), 21 deletions(-)
diff --git a/hw/acpi/viot.c b/hw/acpi/viot.c
index a41daded71..5dafcbf5ef 100644
--- a/hw/acpi/viot.c
+++ b/hw/acpi/viot.c
@@ -16,6 +16,31 @@ struct viot_pci_ranges {
uint16_t output_node;
};
+static void build_pci_host_range(GArray *table_data, int min_bus, int max_bus,
+ uint16_t output_node)
+{
+ /* Type */
+ build_append_int_noprefix(table_data, 1 /* PCI range */, 1);
+ /* Reserved */
+ build_append_int_noprefix(table_data, 0, 1);
+ /* Length */
+ build_append_int_noprefix(table_data, 24, 2);
+ /* Endpoint start */
+ build_append_int_noprefix(table_data, PCI_BUILD_BDF(min_bus, 0), 4);
+ /* PCI Segment start */
+ build_append_int_noprefix(table_data, 0, 2);
+ /* PCI Segment end */
+ build_append_int_noprefix(table_data, 0, 2);
+ /* PCI BDF start */
+ build_append_int_noprefix(table_data, PCI_BUILD_BDF(min_bus, 0), 2);
+ /* PCI BDF end */
+ build_append_int_noprefix(table_data, PCI_BUILD_BDF(max_bus, 0xff), 2);
+ /* Output node */
+ build_append_int_noprefix(table_data, output_node, 2);
+ /* Reserved */
+ build_append_int_noprefix(table_data, 0, 6);
+}
+
/* Build PCI range for a given PCI host bridge */
static int enumerate_pci_host_bridges(Object *obj, void *opaque)
{
@@ -30,27 +55,8 @@ static int enumerate_pci_host_bridges(Object *obj, void
*opaque)
pci_bus_range(bus, &min_bus, &max_bus);
- /* Type */
- build_append_int_noprefix(blob, 1 /* PCI range */, 1);
- /* Reserved */
- build_append_int_noprefix(blob, 0, 1);
- /* Length */
- build_append_int_noprefix(blob, 24, 2);
- /* Endpoint start */
- build_append_int_noprefix(blob, PCI_BUILD_BDF(min_bus, 0), 4);
- /* PCI Segment start */
- build_append_int_noprefix(blob, 0, 2);
- /* PCI Segment end */
- build_append_int_noprefix(blob, 0, 2);
- /* PCI BDF start */
- build_append_int_noprefix(blob, PCI_BUILD_BDF(min_bus, 0), 2);
- /* PCI BDF end */
- build_append_int_noprefix(blob, PCI_BUILD_BDF(max_bus, 0xff), 2);
- /* Output node */
- build_append_int_noprefix(blob, pci_ranges->output_node, 2);
- /* Reserved */
- build_append_int_noprefix(blob, 0, 6);
-
+ build_pci_host_range(blob, min_bus, max_bus,
+ pci_ranges->output_node);
pci_ranges->count++;
}
}
--
MST
- [PULL 37/54] hw/acpi/cxl: Pass in the CXLState directly rather than MachineState, (continued)
- [PULL 37/54] hw/acpi/cxl: Pass in the CXLState directly rather than MachineState, Michael S. Tsirkin, 2022/06/10
- [PULL 40/54] pci/pci_expander_bridge: For CXL HB delay the HB register memory region setup., Michael S. Tsirkin, 2022/06/10
- [PULL 35/54] x86: acpi-build: do not include hw/isa/isa.h directly, Michael S. Tsirkin, 2022/06/10
- [PULL 43/54] hw/machine: Drop cxl_supported flag as no longer useful, Michael S. Tsirkin, 2022/06/10
- [PULL 42/54] hw/cxl: Move the CXLState from MachineState to machine type specific state., Michael S. Tsirkin, 2022/06/10
- [PULL 36/54] hw/cxl: Make the CXL fixed memory window setup a machine parameter., Michael S. Tsirkin, 2022/06/10
- [PULL 41/54] tests/acpi: Update q35/CEDT.cxl for new memory addresses., Michael S. Tsirkin, 2022/06/10
- [PULL 44/54] pci: fix overflow in snprintf string formatting, Michael S. Tsirkin, 2022/06/10
- [PULL 45/54] hw/cxl: Fix missing write mask for HDM decoder target list registers, Michael S. Tsirkin, 2022/06/10
- [PULL 46/54] hw/acpi/viot: rename build_pci_range_node() to enumerate_pci_host_bridges(), Michael S. Tsirkin, 2022/06/10
- [PULL 47/54] hw/acpi/viot: move the individual PCI host bridge entry generation to a new function,
Michael S. Tsirkin <=
- [PULL 48/54] hw/acpi/viot: build array of PCI host bridges before generating VIOT ACPI table, Michael S. Tsirkin, 2022/06/10
- [PULL 49/54] tests/acpi: virt: allow VIOT acpi table changes, Michael S. Tsirkin, 2022/06/10
- [PULL 50/54] hw/acpi/viot: sort VIOT ACPI table entries by PCI host bridge min_bus, Michael S. Tsirkin, 2022/06/10
- [PULL 51/54] tests/acpi: virt: update golden masters for VIOT, Michael S. Tsirkin, 2022/06/10
- [PULL 52/54] hw/virtio/vhost-user: don't use uninitialized variable, Michael S. Tsirkin, 2022/06/10
- [PULL 53/54] hw/vhost-user-scsi|blk: set `supports_config` flag correctly, Michael S. Tsirkin, 2022/06/10
- [PULL 54/54] crypto: Introduce RSA algorithm, Michael S. Tsirkin, 2022/06/10