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[PULL 45/54] hw/cxl: Fix missing write mask for HDM decoder target list
From: |
Michael S. Tsirkin |
Subject: |
[PULL 45/54] hw/cxl: Fix missing write mask for HDM decoder target list registers |
Date: |
Fri, 10 Jun 2022 03:59:16 -0400 |
From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Without being able to write these registers, no interleaving is possible.
More refined checks of HDM register state on commit to follow.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Message-Id: <20220608130804.25795-1-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/cxl/cxl-component-utils.c | 13 +++++++++++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/hw/cxl/cxl-component-utils.c b/hw/cxl/cxl-component-utils.c
index 7985c9bfca..3edd303a33 100644
--- a/hw/cxl/cxl-component-utils.c
+++ b/hw/cxl/cxl-component-utils.c
@@ -154,7 +154,8 @@ static void ras_init_common(uint32_t *reg_state, uint32_t
*write_msk)
reg_state[R_CXL_RAS_ERR_CAP_CTRL] = 0x00;
}
-static void hdm_init_common(uint32_t *reg_state, uint32_t *write_msk)
+static void hdm_init_common(uint32_t *reg_state, uint32_t *write_msk,
+ enum reg_type type)
{
int decoder_count = 1;
int i;
@@ -174,6 +175,14 @@ static void hdm_init_common(uint32_t *reg_state, uint32_t
*write_msk)
write_msk[R_CXL_HDM_DECODER0_SIZE_LO + i * 0x20] = 0xf0000000;
write_msk[R_CXL_HDM_DECODER0_SIZE_HI + i * 0x20] = 0xffffffff;
write_msk[R_CXL_HDM_DECODER0_CTRL + i * 0x20] = 0x13ff;
+ if (type == CXL2_DEVICE ||
+ type == CXL2_TYPE3_DEVICE ||
+ type == CXL2_LOGICAL_DEVICE) {
+ write_msk[R_CXL_HDM_DECODER0_TARGET_LIST_LO + i * 0x20] =
0xf0000000;
+ } else {
+ write_msk[R_CXL_HDM_DECODER0_TARGET_LIST_LO + i * 0x20] =
0xffffffff;
+ }
+ write_msk[R_CXL_HDM_DECODER0_TARGET_LIST_HI + i * 0x20] = 0xffffffff;
}
}
@@ -239,7 +248,7 @@ void cxl_component_register_init_common(uint32_t
*reg_state, uint32_t *write_msk
}
init_cap_reg(HDM, 5, 1);
- hdm_init_common(reg_state, write_msk);
+ hdm_init_common(reg_state, write_msk, type);
if (caps < 5) {
return;
--
MST
- [PULL 38/54] hw/cxl: Push linking of CXL targets into i386/pc rather than in machine.c, (continued)
- [PULL 38/54] hw/cxl: Push linking of CXL targets into i386/pc rather than in machine.c, Michael S. Tsirkin, 2022/06/10
- [PULL 39/54] tests/acpi: Allow modification of q35 CXL CEDT table., Michael S. Tsirkin, 2022/06/10
- [PULL 37/54] hw/acpi/cxl: Pass in the CXLState directly rather than MachineState, Michael S. Tsirkin, 2022/06/10
- [PULL 40/54] pci/pci_expander_bridge: For CXL HB delay the HB register memory region setup., Michael S. Tsirkin, 2022/06/10
- [PULL 35/54] x86: acpi-build: do not include hw/isa/isa.h directly, Michael S. Tsirkin, 2022/06/10
- [PULL 43/54] hw/machine: Drop cxl_supported flag as no longer useful, Michael S. Tsirkin, 2022/06/10
- [PULL 42/54] hw/cxl: Move the CXLState from MachineState to machine type specific state., Michael S. Tsirkin, 2022/06/10
- [PULL 36/54] hw/cxl: Make the CXL fixed memory window setup a machine parameter., Michael S. Tsirkin, 2022/06/10
- [PULL 41/54] tests/acpi: Update q35/CEDT.cxl for new memory addresses., Michael S. Tsirkin, 2022/06/10
- [PULL 44/54] pci: fix overflow in snprintf string formatting, Michael S. Tsirkin, 2022/06/10
- [PULL 45/54] hw/cxl: Fix missing write mask for HDM decoder target list registers,
Michael S. Tsirkin <=
- [PULL 46/54] hw/acpi/viot: rename build_pci_range_node() to enumerate_pci_host_bridges(), Michael S. Tsirkin, 2022/06/10
- [PULL 47/54] hw/acpi/viot: move the individual PCI host bridge entry generation to a new function, Michael S. Tsirkin, 2022/06/10
- [PULL 48/54] hw/acpi/viot: build array of PCI host bridges before generating VIOT ACPI table, Michael S. Tsirkin, 2022/06/10
- [PULL 49/54] tests/acpi: virt: allow VIOT acpi table changes, Michael S. Tsirkin, 2022/06/10
- [PULL 50/54] hw/acpi/viot: sort VIOT ACPI table entries by PCI host bridge min_bus, Michael S. Tsirkin, 2022/06/10
- [PULL 51/54] tests/acpi: virt: update golden masters for VIOT, Michael S. Tsirkin, 2022/06/10
- [PULL 52/54] hw/virtio/vhost-user: don't use uninitialized variable, Michael S. Tsirkin, 2022/06/10
- [PULL 53/54] hw/vhost-user-scsi|blk: set `supports_config` flag correctly, Michael S. Tsirkin, 2022/06/10
- [PULL 54/54] crypto: Introduce RSA algorithm, Michael S. Tsirkin, 2022/06/10