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[PATCH qemu.git v3 3/8] hw/timer/imx_epit: define SR_OCIF
From: |
~axelheider |
Subject: |
[PATCH qemu.git v3 3/8] hw/timer/imx_epit: define SR_OCIF |
Date: |
Sat, 19 Nov 2022 15:59:40 +0100 |
From: Axel Heider <axel.heider@hensoldt.net>
---
hw/timer/imx_epit.c | 12 ++++++------
include/hw/timer/imx_epit.h | 2 ++
2 files changed, 8 insertions(+), 6 deletions(-)
diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c
index 661e9158e3..f148868b8c 100644
--- a/hw/timer/imx_epit.c
+++ b/hw/timer/imx_epit.c
@@ -66,7 +66,7 @@ static const IMXClk imx_epit_clocks[] = {
*/
static void imx_epit_update_int(IMXEPITState *s)
{
- if (s->sr && (s->cr & CR_OCIEN) && (s->cr & CR_EN)) {
+ if ((s->sr & SR_OCIF) && (s->cr & CR_OCIEN) && (s->cr & CR_EN)) {
qemu_irq_raise(s->irq);
} else {
qemu_irq_lower(s->irq);
@@ -256,9 +256,9 @@ static void imx_epit_write(void *opaque, hwaddr offset,
uint64_t value,
break;
case 1: /* SR - ACK*/
- /* writing 1 to OCIF clears the OCIF bit */
- if (value & 0x01) {
- s->sr = 0;
+ /* writing 1 to SR.OCIF clears this bit and turns the interrupt off */
+ if (value & SR_OCIF) {
+ s->sr = 0; /* SR.OCIF is the only bit in this register anyway */
imx_epit_update_int(s);
}
break;
@@ -309,8 +309,8 @@ static void imx_epit_cmp(void *opaque)
IMXEPITState *s = IMX_EPIT(opaque);
DPRINTF("sr was %d\n", s->sr);
-
- s->sr = 1;
+ /* Set interrupt status bit SR.OCIF and update the interrupt state */
+ s->sr |= SR_OCIF;
imx_epit_update_int(s);
}
diff --git a/include/hw/timer/imx_epit.h b/include/hw/timer/imx_epit.h
index e2cb96229b..783eaf0c3a 100644
--- a/include/hw/timer/imx_epit.h
+++ b/include/hw/timer/imx_epit.h
@@ -53,6 +53,8 @@
#define CR_CLKSRC_SHIFT (24)
#define CR_CLKSRC_BITS (2)
+#define SR_OCIF (1 << 0)
+
#define EPIT_TIMER_MAX 0XFFFFFFFFUL
#define TYPE_IMX_EPIT "imx.epit"
--
2.34.5
- [PATCH qemu.git v3 0/8] hw/timer/imx_epit: improve and fix EPIT compare timer, ~axelheider, 2022/12/01
- [PATCH qemu.git v3 4/8] hw/timer/imx_epit: update interrupt state on CR write access, ~axelheider, 2022/12/01
- [PATCH qemu.git v3 3/8] hw/timer/imx_epit: define SR_OCIF,
~axelheider <=
- [PATCH qemu.git v3 8/8] hw/timer/imx_epit: fix compare timer handling, ~axelheider, 2022/12/01
- [PATCH qemu.git v3 5/8] hw/timer/imx_epit: hard reset initializes CR with 0, ~axelheider, 2022/12/01
- [PATCH qemu.git v3 6/8] hw/timer/imx_epit: factor out register write handlers, ~axelheider, 2022/12/01
- [PATCH qemu.git v3 2/8] hw/timer/imx_epit: cleanup CR defines, ~axelheider, 2022/12/01
- [PATCH qemu.git v3 1/8] hw/timer/imx_epit: improve comments, ~axelheider, 2022/12/01
- [PATCH qemu.git v3 7/8] hw/timer/imx_epit: remove explicit fields cnt and freq, ~axelheider, 2022/12/01