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[PATCH qemu.git v3 1/8] hw/timer/imx_epit: improve comments
From: |
~axelheider |
Subject: |
[PATCH qemu.git v3 1/8] hw/timer/imx_epit: improve comments |
Date: |
Thu, 01 Dec 2022 15:42:05 -0000 |
From: Axel Heider <axel.heider@hensoldt.net>
Fix typos, add background information
Signed-off-by: Axel Heider <axel.heider@hensoldt.net>
---
hw/timer/imx_epit.c | 20 ++++++++++++++++----
1 file changed, 16 insertions(+), 4 deletions(-)
diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c
index ec0fa440d7..2841fbaa1c 100644
--- a/hw/timer/imx_epit.c
+++ b/hw/timer/imx_epit.c
@@ -96,13 +96,14 @@ static void imx_epit_set_freq(IMXEPITState *s)
}
}
+/*
+ * This is called both on hardware (device) reset and software reset.
+ */
static void imx_epit_reset(DeviceState *dev)
{
IMXEPITState *s = IMX_EPIT(dev);
- /*
- * Soft reset doesn't touch some bits; hard reset clears them
- */
+ /* Soft reset doesn't touch some bits; hard reset clears them */
s->cr &= (CR_EN|CR_ENMOD|CR_STOPEN|CR_DOZEN|CR_WAITEN|CR_DBGEN);
s->sr = 0;
s->lr = EPIT_TIMER_MAX;
@@ -214,6 +215,7 @@ static void imx_epit_write(void *opaque, hwaddr offset,
uint64_t value,
ptimer_transaction_begin(s->timer_cmp);
ptimer_transaction_begin(s->timer_reload);
+ /* Update the frequency. Has been done already in case of a reset. */
if (!(s->cr & CR_SWR)) {
imx_epit_set_freq(s);
}
@@ -254,7 +256,7 @@ static void imx_epit_write(void *opaque, hwaddr offset,
uint64_t value,
break;
case 1: /* SR - ACK*/
- /* writing 1 to OCIF clear the OCIF bit */
+ /* writing 1 to OCIF clears the OCIF bit */
if (value & 0x01) {
s->sr = 0;
imx_epit_update_int(s);
@@ -352,8 +354,18 @@ static void imx_epit_realize(DeviceState *dev, Error
**errp)
0x00001000);
sysbus_init_mmio(sbd, &s->iomem);
+ /*
+ * The reload timer keeps running when the peripheral is enabled. It is a
+ * kind of wall clock that does not generate any interrupts. The callback
+ * needs to be provided, but it does nothing as the ptimer already supports
+ * all necessary reloading functionality.
+ */
s->timer_reload = ptimer_init(imx_epit_reload, s, PTIMER_POLICY_LEGACY);
+ /*
+ * The compare timer is running only when the peripheral configuration is
+ * in a state that will generate compare interrupts.
+ */
s->timer_cmp = ptimer_init(imx_epit_cmp, s, PTIMER_POLICY_LEGACY);
}
--
2.34.5
- [PATCH qemu.git v3 0/8] hw/timer/imx_epit: improve and fix EPIT compare timer, ~axelheider, 2022/12/01
- [PATCH qemu.git v3 4/8] hw/timer/imx_epit: update interrupt state on CR write access, ~axelheider, 2022/12/01
- [PATCH qemu.git v3 3/8] hw/timer/imx_epit: define SR_OCIF, ~axelheider, 2022/12/01
- [PATCH qemu.git v3 8/8] hw/timer/imx_epit: fix compare timer handling, ~axelheider, 2022/12/01
- [PATCH qemu.git v3 5/8] hw/timer/imx_epit: hard reset initializes CR with 0, ~axelheider, 2022/12/01
- [PATCH qemu.git v3 6/8] hw/timer/imx_epit: factor out register write handlers, ~axelheider, 2022/12/01
- [PATCH qemu.git v3 2/8] hw/timer/imx_epit: cleanup CR defines, ~axelheider, 2022/12/01
- [PATCH qemu.git v3 1/8] hw/timer/imx_epit: improve comments,
~axelheider <=
- [PATCH qemu.git v3 7/8] hw/timer/imx_epit: remove explicit fields cnt and freq, ~axelheider, 2022/12/01