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[PATCH v4 15/27] tcg/s390x: Support MIE2 MGRK instruction
From: |
Richard Henderson |
Subject: |
[PATCH v4 15/27] tcg/s390x: Support MIE2 MGRK instruction |
Date: |
Thu, 8 Dec 2022 20:05:18 -0600 |
The MIE2 facility adds a 3-operand signed 64x64->128 multiply.
Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/s390x/tcg-target-con-set.h | 1 +
tcg/s390x/tcg-target.h | 2 +-
tcg/s390x/tcg-target.c.inc | 8 ++++++++
3 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/tcg/s390x/tcg-target-con-set.h b/tcg/s390x/tcg-target-con-set.h
index 33a82e3286..b1a89a88ba 100644
--- a/tcg/s390x/tcg-target-con-set.h
+++ b/tcg/s390x/tcg-target-con-set.h
@@ -31,6 +31,7 @@ C_O1_I3(v, v, v, v)
C_O1_I4(r, r, ri, r, 0)
C_O1_I4(r, r, ri, rI, 0)
C_O2_I2(o, m, 0, r)
+C_O2_I2(o, m, r, r)
C_O2_I3(o, m, 0, 1, r)
C_O2_I4(r, r, 0, 1, rA, r)
C_O2_I4(r, r, 0, 1, ri, r)
diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h
index 1fb7b8fb1d..03ce11a34a 100644
--- a/tcg/s390x/tcg-target.h
+++ b/tcg/s390x/tcg-target.h
@@ -136,7 +136,7 @@ extern uint64_t s390_facilities[3];
#define TCG_TARGET_HAS_add2_i64 1
#define TCG_TARGET_HAS_sub2_i64 1
#define TCG_TARGET_HAS_mulu2_i64 1
-#define TCG_TARGET_HAS_muls2_i64 0
+#define TCG_TARGET_HAS_muls2_i64 HAVE_FACILITY(MISC_INSN_EXT2)
#define TCG_TARGET_HAS_muluh_i64 0
#define TCG_TARGET_HAS_mulsh_i64 0
diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc
index 9634126ed1..871fcb7683 100644
--- a/tcg/s390x/tcg-target.c.inc
+++ b/tcg/s390x/tcg-target.c.inc
@@ -175,6 +175,7 @@ typedef enum S390Opcode {
RRE_SLBGR = 0xb989,
RRE_XGR = 0xb982,
+ RRFa_MGRK = 0xb9ec,
RRFa_MSRKC = 0xb9fd,
RRFa_MSGRKC = 0xb9ed,
RRFa_NRK = 0xb9f4,
@@ -2319,6 +2320,11 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode
opc,
tcg_debug_assert(args[0] == args[1] + 1);
tcg_out_insn(s, RRE, MLGR, args[1], args[3]);
break;
+ case INDEX_op_muls2_i64:
+ tcg_debug_assert((args[1] & 1) == 0);
+ tcg_debug_assert(args[0] == args[1] + 1);
+ tcg_out_insn(s, RRFa, MGRK, args[1], args[2], args[3]);
+ break;
case INDEX_op_shl_i64:
op = RSY_SLLG;
@@ -3009,6 +3015,8 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode
op)
case INDEX_op_mulu2_i64:
return C_O2_I2(o, m, 0, r);
+ case INDEX_op_muls2_i64:
+ return C_O2_I2(o, m, r, r);
case INDEX_op_add2_i32:
case INDEX_op_sub2_i32:
--
2.34.1
- Re: [PATCH v4 07/27] tcg/s390x: Check for general-instruction-extension facility at startup, (continued)
- [PATCH v4 09/27] tcg/s390x: Remove FAST_BCR_SER facility check, Richard Henderson, 2022/12/08
- [PATCH v4 10/27] tcg/s390x: Remove DISTINCT_OPERANDS facility check, Richard Henderson, 2022/12/08
- [PATCH v4 11/27] tcg/s390x: Use LARL+AGHI for odd addresses, Richard Henderson, 2022/12/08
- [PATCH v4 12/27] tcg/s390x: Distinguish RRF-a and RRF-c formats, Richard Henderson, 2022/12/08
- [PATCH v4 13/27] tcg/s390x: Distinguish RIE formats, Richard Henderson, 2022/12/08
- [PATCH v4 16/27] tcg/s390x: Issue XILF directly for xor_i32, Richard Henderson, 2022/12/08
- [PATCH v4 15/27] tcg/s390x: Support MIE2 MGRK instruction,
Richard Henderson <=
- [PATCH v4 17/27] tcg/s390x: Tighten constraints for or_i64 and xor_i64, Richard Henderson, 2022/12/08
- [PATCH v4 18/27] tcg/s390x: Tighten constraints for and_i64, Richard Henderson, 2022/12/08
- [PATCH v4 19/27] tcg/s390x: Support MIE3 logical operations, Richard Henderson, 2022/12/08
- [PATCH v4 14/27] tcg/s390x: Support MIE2 multiply single instructions, Richard Henderson, 2022/12/08
- [PATCH v4 20/27] tcg/s390x: Create tgen_cmp2 to simplify movcond, Richard Henderson, 2022/12/08
- [PATCH v4 21/27] tcg/s390x: Generalize movcond implementation, Richard Henderson, 2022/12/08
- [PATCH v4 22/27] tcg/s390x: Support SELGR instruction in movcond, Richard Henderson, 2022/12/08
- [PATCH v4 23/27] tcg/s390x: Use tgen_movcond_int in tgen_clz, Richard Henderson, 2022/12/08