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[PULL 16/29] target/arm: Report FEAT_EVT for TCG '-cpu max'
From: |
Peter Maydell |
Subject: |
[PULL 16/29] target/arm: Report FEAT_EVT for TCG '-cpu max' |
Date: |
Thu, 15 Dec 2022 12:49:56 +0000 |
Update the ID registers for TCG's '-cpu max' to report the
FEAT_EVT Enhanced Virtualization Traps support.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
docs/system/arm/emulation.rst | 1 +
target/arm/cpu64.c | 1 +
target/arm/cpu_tcg.c | 1 +
3 files changed, 3 insertions(+)
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
index e3af79bb8c9..b33d7c28dc1 100644
--- a/docs/system/arm/emulation.rst
+++ b/docs/system/arm/emulation.rst
@@ -26,6 +26,7 @@ the following architecture extensions:
- FEAT_DoubleFault (Double Fault Extension)
- FEAT_E0PD (Preventing EL0 access to halves of address maps)
- FEAT_ETS (Enhanced Translation Synchronization)
+- FEAT_EVT (Enhanced Virtualization Traps)
- FEAT_FCMA (Floating-point complex number instructions)
- FEAT_FHM (Floating-point half-precision multiplication instructions)
- FEAT_FP16 (Half-precision floating-point data processing)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index cec64471b4e..2cf2ca4ce5a 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -1254,6 +1254,7 @@ static void aarch64_max_initfn(Object *obj)
t = FIELD_DP64(t, ID_AA64MMFR2, FWB, 1); /* FEAT_S2FWB */
t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */
t = FIELD_DP64(t, ID_AA64MMFR2, BBM, 2); /* FEAT_BBM at level 2 */
+ t = FIELD_DP64(t, ID_AA64MMFR2, EVT, 2); /* FEAT_EVT */
t = FIELD_DP64(t, ID_AA64MMFR2, E0PD, 1); /* FEAT_E0PD */
cpu->isar.id_aa64mmfr2 = t;
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
index 9a2cef7d05a..568cbcfc524 100644
--- a/target/arm/cpu_tcg.c
+++ b/target/arm/cpu_tcg.c
@@ -65,6 +65,7 @@ void aa32_max_features(ARMCPU *cpu)
t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* FEAT_TTCNP */
t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* FEAT_XNX */
+ t = FIELD_DP32(t, ID_MMFR4, EVT, 2); /* FEAT_EVT */
cpu->isar.id_mmfr4 = t;
t = cpu->isar.id_mmfr5;
--
2.25.1
- [PULL 14/29] target/arm: Implement HCR_EL2.TICAB,TOCU traps, (continued)
- [PULL 14/29] target/arm: Implement HCR_EL2.TICAB,TOCU traps, Peter Maydell, 2022/12/15
- [PULL 21/29] hw/intc: Convert TYPE_ARM_GICV3_COMMON to 3-phase reset, Peter Maydell, 2022/12/15
- [PULL 19/29] hw/intc: Convert TYPE_ARM_GIC_COMMON to 3-phase reset, Peter Maydell, 2022/12/15
- [PULL 08/29] hw/arm/virt: build SMBIOS 19 table, Peter Maydell, 2022/12/15
- [PULL 29/29] target/arm: Restrict arm_cpu_exec_interrupt() to TCG accelerator, Peter Maydell, 2022/12/15
- [PULL 22/29] hw/intc: Convert TYPE_KVM_ARM_GICV3 to 3-phase reset, Peter Maydell, 2022/12/15
- [PULL 23/29] hw/intc: Convert TYPE_ARM_GICV3_ITS_COMMON to 3-phase reset, Peter Maydell, 2022/12/15
- [PULL 28/29] hw/misc: Move some arm-related files from specific_ss into softmmu_ss, Peter Maydell, 2022/12/15
- [PULL 25/29] hw/intc: Convert TYPE_KVM_ARM_ITS to 3-phase reset, Peter Maydell, 2022/12/15
- [PULL 18/29] hw/arm: Convert TYPE_ARM_SMMUV3 to 3-phase reset, Peter Maydell, 2022/12/15
- [PULL 16/29] target/arm: Report FEAT_EVT for TCG '-cpu max',
Peter Maydell <=
- [PULL 20/29] hw/intc: Convert TYPE_ARM_GIC_KVM to 3-phase reset, Peter Maydell, 2022/12/15
- [PULL 24/29] hw/intc: Convert TYPE_ARM_GICV3_ITS to 3-phase reset, Peter Maydell, 2022/12/15
- [PULL 26/29] hw/arm/boot: set initrd with #address-cells type in fdt, Peter Maydell, 2022/12/15
- [PULL 27/29] target/arm: align exposed ID registers with Linux, Peter Maydell, 2022/12/15